Top Tech Jobs & Startup Jobs

Reposted 14 Days AgoSaved
Hybrid
New York, NY, USA
115K-190K Annually
Senior level
115K-190K Annually
Senior level
Artificial Intelligence • Hardware • Healthtech • Machine Learning • Wearables
Drive commercial expansion for brick-and-mortar locations end-to-end: market research, site selection, lease support, launch coordination, stakeholder management, experiments on new service models, and data-driven recommendations. Regular travel to support launches and on-the-ground operations.
Reposted 14 Days AgoSaved
Hybrid
New York, NY, USA
160K-200K Annually
Senior level
160K-200K Annually
Senior level
Artificial Intelligence • Hardware • Healthtech • Machine Learning • Wearables
Lead RF development and bring-up for ear-worn hearing aid products: design antenna and matching networks, optimize link budgets for Bluetooth/BLE/NFMI, collaborate on schematic and PCB layout (Altium), run RF simulation and bench/chamber testing (CST Studio and RF test gear), prototype and troubleshoot, and support production validation and regulatory testing.
Top Skills: AltiumBluetooth ClassicBluetooth Low Energy (Ble)Cst StudioNetwork AnalyzerNfmiOscilloscopeRf Bench ToolsSpectrum Analyzer
Reposted 14 Days AgoSaved
Hybrid
New York, NY, USA
140K-200K Annually
Senior level
140K-200K Annually
Senior level
Artificial Intelligence • Hardware • Healthtech • Machine Learning • Wearables
Lead and evolve Fortell's visual brand strategy across digital, print, in-clinic, and OOH channels. Produce conversion-driving designs for website, email, social, ads, and physical environments. Direct creative concepting, quality-control consumer-facing work, and manage external agencies while championing accessible, empathetic, and consistent brand expression.
Reposted 14 Days AgoSaved
In-Office or Remote
8 Locations
160K-300K Annually
Expert/Leader
160K-300K Annually
Expert/Leader
Artificial Intelligence • Hardware • Healthtech • Machine Learning • Wearables
Lead full-chip DFT architecture and implementation including scan, compression, MBIST/BIST, ATPG vector generation, gate-level verification, and silicon debug. Collaborate with STA, physical design, memory compiler, and test teams to ensure production-ready silicon with high test coverage and diagnostic capability, and support bring-up and debug on silicon.
Top Skills: AtpgBistBoundary ScanCadence GenusCadence ModusCompression LogicGate-Level SimulationJtagMbistMemory CompilerScan ChainsSilicon DebugTcl
Reposted 29 Days AgoSaved
In-Office or Remote
8 Locations
150K-250K Annually
Senior level
150K-250K Annually
Senior level
Artificial Intelligence • Hardware • Healthtech • Machine Learning • Wearables
Execute synthesis, place-and-route and STA for ASIC partitions from RTL to silicon. Collaborate with architects, RTL designers and DFT engineers to close EM/IR, LEC and physical verification signoff. Improve physical design methodologies (synthesis, PnR, EMIR, PDN), troubleshoot flows and work with EDA vendors to resolve issues while meeting tight schedules and low-power goals.
Top Skills: CadenceEm/IrInnovusLogical Equivalence Checking (Lec)Place And Route (Pnr)Power Delivery Network (Pdn)QuantusRtlSocStatic Timing Analysis (Sta)Sub-7NmSynopsysSynthesisTclTempus
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