Fortell is building breakthrough AI-powered hearing technology that redefines how people experience sound and connect with the world. Powered by custom silicon and advances in hearing science, our hearing aids help people hear, and live, with greater clarity and confidence.
We’re looking for an experienced DFT Engineer to lead full-chip test architecture, from scan and compression logic to MBIST and silicon debug. You’ll collaborate across STA, physical design, memory, and test teams to deliver production-ready silicon with world-class test coverage and diagnostic capability.
Job Responsibilities:
Develop, architect and implement comprehensive DFT structures tailored to specific design requirements, including full-scan, boundary scan, and memory test strategies.
Design and implement robust DFT infrastructure, including scan chains, compression logic, MBIST, BIST, JTAG, and other test mechanisms.
Generate high-quality ATPG test vectors for logic and memory, and analyze DFT coverage to ensure thorough fault detection and diagnostic capability.
Perform MBIST verification including simulation of memory test algorithms, fault modeling, and debug of failing patterns.
Verify test patterns using gate-level simulations to identify and address functional or timing-related issues.
Collaborate closely with STA, physical design, power, and memory compiler teams to debug and resolve DFT/MBIST-related challenges.
Work in partnership with test engineers to bring up scan and MBIST vectors on silicon, support silicon debug, and ensure successful production testing.
Preferred Qualifications:
Strong understanding of industry standards and best practices in DFT, ATPG, JTAG, and MBIST.
Proven experience in developing DFT specifications and architectures for complex designs.
Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more.
Proficiency in Cadence tools like Modus and Genus for DFT implementation, vector generation, and verification.
Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes.
Efficient scripting skills using TCL for automating tasks and developing custom flows.
Candidates must reside in the Bay Area and be available for occasional in-person collaboration, with plans to establish a local office in the future. Occasional travel to other company locations may be required.
The target base salary range for this position is $160,000–$300,000 annually, with actual compensation determined by level, experience, and qualifications. Total compensation includes stock options and a generous benefits package.
Skills Required
- Design and implement full-chip DFT structures including full-scan, boundary scan, and memory test strategies.
- Develop scan chains, compression logic, MBIST/BIST, JTAG and other test mechanisms.
- Generate and analyze ATPG test vectors for logic and memory to ensure coverage and diagnostic capability.
- Perform MBIST verification, memory test algorithm simulation, fault modeling, and debug failing patterns.
- Verify test patterns using gate-level simulations to identify functional or timing issues.
- Collaborate with STA, physical design, power, and memory compiler teams to debug and resolve DFT/MBIST issues.
- Support silicon bring-up, assist test engineers with scan and MBIST vectors, and lead silicon debug efforts.
- Must reside in the Bay Area and be available for occasional in-person collaboration.
- Strong understanding of DFT industry standards and best practices (ATPG, JTAG, MBIST).
- Proficiency with Cadence tools such as Modus and Genus for DFT implementation and vector generation.
- Efficient scripting skills, particularly TCL, to automate tasks and build custom flows.
- Proven experience developing DFT specifications and architectures for complex designs and debugging DFT issues.
What We Do
Fortell is building breakthrough AI-powered hearing technology that redefines how people experience sound and connect with the world.
