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The Physical Design Engineer will manage SOC physical assembly, design methodologies, and collaborate with engineers to optimize performance, power, and area for AI infrastructure solutions.

Lead the QA strategy for Network SDK, design test frameworks, mentor engineers, validate core SDK layers, and ensure high-quality releases.

Lead the design and development of SDK for Eridu's switch ASICs, ensuring performance and production readiness. Oversee software interfaces for dataplane operations and mentor junior engineers.

Lead the development and integration of OCP SAI with SONiC, requiring expertise in programming, SDK development, and networking protocols.

Develop verification infrastructure, perform ASIC verification, execute simulations, analyze coverage metrics, and ensure quality assurance processes.

The Hardware Engineer will design, validate, and deliver systems and sub-assemblies for AI infrastructure, collaborating across multiple teams to ensure effective product development.