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The Substrate Layout Design Engineer will develop advanced multi-die organic flip chip modules, focusing on substrate layout, routing feasibility, and collaboration with packaging and mechanical teams for manufacturability and performance optimization.

Lead the architecture and implementation of high-performance packet processing pipelines for networking ASICs. Collaborate with cross-functional teams on chip design, performance modeling, and validation.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.

The ASIC Architect will translate system requirements into detailed architecture, guide modeling and feasibility analysis, and collaborate for seamless design implementation across teams for Eridu's networking products.

The role involves post-silicon bring-up, debugging, and validation of ASICs, focusing on diagnostic infrastructures and automation frameworks.

Lead ASIC chip design from micro-architecture to full-chip integration, emphasizing RTL development, verification collaboration, and timing closure.

Lead the simulation and analysis of AI communication workloads, optimizing performance and collaborating with customers and ASIC designers to enhance AI networking solutions.

The Physical Design Engineer will manage SOC physical assembly, design methodologies, and collaborate with engineers to optimize performance, power, and area for AI infrastructure solutions.