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Lead the architecture and implementation of high-performance packet processing pipelines for networking ASICs. Collaborate with cross-functional teams on chip design, performance modeling, and validation.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

The ASIC Architect will translate system requirements into detailed architecture, guide modeling and feasibility analysis, and collaborate for seamless design implementation across teams for Eridu's networking products.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.

The role involves post-silicon bring-up, debugging, and validation of ASICs, focusing on diagnostic infrastructures and automation frameworks.

Lead ASIC chip design from micro-architecture to full-chip integration, emphasizing RTL development, verification collaboration, and timing closure.

Lead the simulation and analysis of AI communication workloads, optimizing performance and collaborating with customers and ASIC designers to enhance AI networking solutions.

Hands-on lab intern supporting engineering operations: maintain and install lab equipment, assemble systems, configure switches and Layer 2/LAN networking, assist with power, cabling, troubleshooting, inventory, and documentation while collaborating with engineers.

The role involves defining, architecting, and implementing high-speed Networking ASICs, focusing on design, testing, performance optimization, and troubleshooting for AI applications.

This listing collects unsolicited applications into a talent pool for future openings at Eridu AI. Candidates submit their information; the company will contact applicants if a role matches their skills and interests.