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The role involves contributing to the development of AI infrastructure solutions that enhance performance in AI data centers, focusing on silicon, software, and system innovations.

Lead DFT architecture for multi-chip systems SOC, managing test design functions and supervising ATPG generation while ensuring performance standards.

The role involves defining, architecting, and implementing high-speed Networking ASICs, focusing on design, testing, performance optimization, and troubleshooting for AI applications.

The Hardware Engineer will design, validate, and deliver systems and sub-assemblies for AI infrastructure, collaborating across multiple teams to ensure effective product development.

Seeking a Senior Power Engineer to design high-efficiency power delivery solutions for AI infrastructure, focusing on DC-DC conversion and power distribution for high-performance systems.

Develop verification infrastructure, perform ASIC verification, execute simulations, analyze coverage metrics, and ensure quality assurance processes.

The Engineering Program Manager will lead complex product development programs, manage cross-functional execution, coordinate schedules, and drive communication among teams and external partners.

The Substrate Layout Design Engineer will develop advanced multi-die organic flip chip modules, focusing on substrate layout, routing feasibility, and collaboration with packaging and mechanical teams for manufacturability and performance optimization.

Lead the architecture and implementation of high-performance packet processing pipelines for networking ASICs. Collaborate with cross-functional teams on chip design, performance modeling, and validation.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.