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The Substrate Layout Design Engineer will develop advanced multi-die organic flip chip modules, focusing on substrate layout, routing feasibility, and collaboration with packaging and mechanical teams for manufacturability and performance optimization.

The role involves developing predictive models for complex mechanical systems, conducting simulations, validating experiments, and leading mechanical design for semiconductor packaging. Responsibilities include material selection, cross-functional collaboration, and influencing system architectures.

Lead the architecture and implementation of high-performance packet processing pipelines for networking ASICs. Collaborate with cross-functional teams on chip design, performance modeling, and validation.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

The Hardware Engineer will design, validate, and deliver systems and sub-assemblies for AI infrastructure, collaborating across multiple teams to ensure effective product development.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.

The ASIC Architect will translate system requirements into detailed architecture, guide modeling and feasibility analysis, and collaborate for seamless design implementation across teams for Eridu's networking products.

Lead hardware system development from concept to production, including schematic design, signal integrity analysis, and team management. Collaborate with various teams and oversee project execution.

Lead DFT architecture for multi-chip systems SOC, managing test design functions and supervising ATPG generation while ensuring performance standards.

Lead ASIC chip design from micro-architecture to full-chip integration, emphasizing RTL development, verification collaboration, and timing closure.