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Lead timing activities for subsystems, drive timing closure, develop methodologies, manage I/O budgets, and collaborate with design teams for timing convergence.

As a Sr. Physical Design Tech Lead/Engineer, you will manage backend implementation from RTL/netlist to GDSII for FPGA/SoC. Responsibilities include leading design tasks, PPA optimization, collaboration with teams, and improving design flows.

The Engineering/IT Specialist translates engineering needs into IT infrastructure specifications, interfaces between IT and engineering, and tracks project statuses.