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Design, build, and operate scalable ML pipelines and infrastructure across cloud and on‑prem HPC. Implement MLOps tooling (tracking, registries, feature stores), CI/CD/CT, containerized GPU orchestration, model optimization (LLMs, GNNs, RL), data/versioning pipelines, monitoring, and mentor engineers to productionize ML for EDA and simulation workloads.

The FP&A Manager will lead budgeting and forecasting, provide financial analysis, collaborate with teams, and drive process improvements.

The FPGA Development Tools Engineer will develop synthesis algorithms, optimize performance, and collaborate on compiler toolchains to enhance FPGA capabilities.

Lead and architect AI initiatives, develop large-scale AI/ML systems, mentor teams, and drive engineering excellence across Altera.

Develop and optimize FPGA routing algorithms, enhance the compiler toolchain, analyze design complexities, and collaborate on FPGA design flows.

Lead the definition and design of clocking architectures for FPGA and SoC devices, ensuring robust clock delivery and compliance with timing requirements across high-speed protocols.

Debug, troubleshoot, and resolve customer-reported FPGA/ASIC hardware, board, firmware, and system issues. Lead root-cause analysis and cross-functional corrective actions, coordinate with customers and manufacturing partners (including on-site visits), support product qualification and production ramp, and develop data collection for quality monitoring and continuous improvement.

Develop and own manufacturing test content for FPGA reset/configuration and Secure Device Manager. Implement DFT strategies (scan, ATPG, MBIST, IJTAG), run pre-silicon test simulations, collaborate with RTL/DFT/verification teams, analyze test results and silicon failures, and optimize test time, cost, and yield.

Serve as the technical liaison between IT, Engineering, and Manufacturing to convert engineering needs into IT roadmaps, specs, user stories, and RFCs. Design high-level and component-level infrastructure (network, compute, storage, security, data), validate capacity and resilience, track dependencies and risks, chair working sessions, produce diagrams and decision records, manage backlog and roadmap, and provide status, KPI dashboards, and executive readouts.

Architect and optimize timing and power implementation flows for ASIC/FPGA designs. Lead STA and UPF-based power flows, library generation/characterization, automation infrastructure, and apply ML/AI to improve flow efficiency, debug productivity, and signoff QoR while collaborating across PD, STA, library, and CAD teams.