Top Tech Jobs & Startup Jobs

Lead SOC and block-level physical implementation from floorplan and power intent through final signoff. Drive STA, power integrity, PPA optimization, and physical verification. Integrate and productize ML/AI optimization into PnR flows. Mentor a team of physical designers, lead cross-functional convergence, define methodology and constraints (SDC/UPF), and represent physical design in architecture and tapeout planning.

Lead physical implementation of custom IP and SoC from RTL through GDSII. Execute synthesis, floorplanning, place-and-route, CTS, STA, power, reliability and physical verification. Analyze signoff results, resolve violations, optimize PPA, and develop/automate physical design methodologies while collaborating with RTL, DFT, timing, verification, and CAD teams.

Implement full-chip and block-level physical design for custom IP and SoC from RTL through GDSII. Execute synthesis, floorplanning, place-and-route, CTS, STA, physical verification and signoff. Optimize power, timing, congestion, and PPA, support DFT integration, root-cause issues, automate flows, and mentor junior engineers across multidisciplinary teams.

Lead enterprise compliance for the EU Cyber Resilience Act by translating regulatory obligations into product lifecycle processes, governance, conformity evidence, and metrics. Coordinate cross-functional activities across security, engineering, quality, legal, and product teams; define SBOM and software-component traceability, vulnerability and post-market processes, conformity-assessment frameworks, training, and audit readiness. Monitor regulatory developments and support product classification, technical documentation, and executive reporting.

Lead timing activities for subsystems from implementation through sign-off. Drive block and subsystem timing closure, develop STA methodologies and automation, define I/O timing budgets, run and optimize large MCMM STA, generate/validate ECOs, provide root-cause analysis and timing guidance, and collaborate with RTL, physical design, and full-chip teams.

Drive thermal and electrical characterization and system-level validation of FPGA products, develop DFT and manufacturing test flows (ATPG, MBIST, BIST), analyze silicon and test data to close tester-to-system gaps, optimize yield and test time, and collaborate across design, packaging, manufacturing, and reliability teams.

The role involves verifying design architectures using UVM methodology, creating test cases, and coordinating with cross-functional teams for full coverage verification.

Optimize and transform Workday Recruiting processes: improve recruiter efficiency, streamline approvals and scheduling, build reporting and dashboards, identify automation/AI opportunities, and partner with TA/HR stakeholders to implement scalable recruiting solutions.

Define and drive silicon domain subsystem architecture for next-generation FPGAs, focusing on security (Root of Trust, secure boot), FPGA configuration, microarchitectural features, hardware/software integration, validation/test planning, modeling and simulation, and cross-functional collaboration to deliver secure, high-performance, and power-efficient silicon solutions.

Define end-to-end robotics system architectures across sensing, perception, localization, planning, control and actuation. Lead customer technical engagements, deliver architecture proposals, PoC/prototyping, demos, and market strategy. Produce reference architectures, white papers, and training materials.