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22 Days AgoSaved
In-Office
Greenwich, CT, USA
Mid level
Mid level
Software
Develop and maintain Java-based web applications and single-page applications. Design databases and REST/SOAP web services, work with SQL/PLSQL, AngularJS, jQuery, JSON, and UNIX/Linux environments. Troubleshoot, ensure code quality, and collaborate independently with minimal supervision.
Top Skills: AjaxAngularjsJavaJava ServletsJqueryJSONJspObject-Oriented ProgrammingPl/SqlRestSoapSQLUnix/Linux
22 Days AgoSaved
In-Office
Austin, TX, USA
Mid level
Mid level
Software
Design and implement verification environments and testbenches using SystemVerilog and verification methodologies (UVM/VMM/OVM). Develop tests for CPU/memory subsystems; ARM experience is a plus.
Top Skills: ArmCpu Memory SubsystemOvmSystem VerilogUvmVmm
22 Days AgoSaved
In-Office
San Jose, CA, USA
Junior
Junior
Software
Test wired and over-the-air system performance for wireless connectivity. Perform PHY and RF measurements, calibrate test fixtures, validate and ensure test result accuracy, and write automation scripts to run and analyze performance tests.
Top Skills: 802.11Ac802.11Ax802.11NOscilloscopePerlPhyPythonRfSpectrum AnalyzerVector Signal Analyzer
22 Days AgoSaved
In-Office
San Diego, CA, USA
Entry level
Entry level
Software
Plan and execute system tests for Bluetooth, BLE, and wireless charging; perform log analysis and debugging; optimize performance metrics (stability, latency, throughput, audio); run field and interoperability tests; attend industry test events and liaise with standards bodies.
Top Skills: AndroidBluetoothBluetooth Low Energy (Le)CC++JavaLinuxRfWindowsWireless Charging
22 Days AgoSaved
In-Office
Tempe, AZ, USA
Senior level
Senior level
Software
Design-for-test (DFT) engineer responsible for DFT structures (scan chains, scan compression), generating and analyzing ATPG coverage, optimizing test coverage, and running gate simulation to verify scan patterns for ASICs.
Top Skills: AtpgDftGate SimulationMentor Graphics Dft ToolsScan ChainsScan Compression
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22 Days AgoSaved
In-Office
San Diego, CA, USA
Mid level
Mid level
Software
Perform formal and functional verification for ASIC/digital designs using assertion languages (SVA/SystemVerilog), EDA formal tools, and verification methodologies. Develop scripts and automation using shell, Perl, Java, and manage revisions with CVS/DesignSync/Subversion. Collaborate on verification plans and use C/C++/SystemC as needed.
Top Skills: 0-InCC++CvsDesignsyncFormal VerificationIfvIusJasperJavaMakefileModelsimOnespinPerlSlecSubversionSystem VerilogSystem Verilog Assertions (Sva)SystemcUnix/Linux ShellVcsVerilogVhdlXMLXml DomXpathXslt
22 Days AgoSaved
In-Office
San Diego, CA, USA
Senior level
Senior level
Software
Lead end-to-end technology integration for client mergers/acquisitions into Hardware Engineering Compute. Manage stakeholders, steering committees, budgets, change management, communications, scope, and delivery across multiple workstreams.
22 Days AgoSaved
In-Office
San Jose, CA, USA
Mid level
Mid level
Software
Develop demo applications for Mac and iPhone, create user-space libraries, and build command-line tools to control drivers and device firmware/hardware. Work primarily on Apple platforms using Objective-C/Swift, with C/C++ development; Python is a plus.
Top Skills: CC++iOSmacOSObjective-CPythonSwift
22 Days AgoSaved
In-Office
San Diego, CA, USA
Senior level
Senior level
Software
Design and verify microarchitecture and RTL for high-speed PHYs and datapaths. Perform timing closure, timing constraints, PTSI, DFT insertion, and STA. Build HVL-based testbenches, linting and synthesis flows, and work with high-speed IO blocks (PLLs, DLLs, LDOs). Apply low-power techniques and collaborate across distributed teams.
Top Skills: Cmos ProcessesDft InsertionDllsHvlsLdosLintingLpddr3Lpddr4PhyPllsStaSynthesisSystemverilogTestbench ArchitecturesVerilog
22 Days AgoSaved
In-Office
San Diego, CA, USA
Mid level
Mid level
Software
Perform physical implementation (place-and-route) and P&R experiments for Adreno GPU cores, including floorplanning, macro placement, CTS, routing, timing closure, STA, low-power (UPF/CPF) flows, physical verification (Calibre DRC/LVS/ERC), and automation scripting to validate new flows and methodologies.
Top Skills: Cadence InnovusCalibreClock Tree Synthesis (Cts)Clp/FvCpfDrcErcGdsiiLvsPerlPlace And Route (P&R)PythonShellStatic Timing Analysis (Sta)Synopsys Icc2Synopsys Primetime SiTempusUpf
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