About Mirafra :
Mirafra is software service base organization started in 2004.
We are 500+ employees in India and 250+ In US
Clear visibility to senior management which helps for constant professional growth
Title : Physical Design Engineer
Location : San Diego,CA
Type : Full Time
Job Overview:
To do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well as Top level MSM. Work On PD projects.
Minimum Qualifications:
Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure Must be able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification.
Tools: EDA Physical design tools experience ( Examples: Cadence Innovas,
Synopsys ICC2, PrimetimeSi/Calibre/ etc)
Skills: Physical design implementation expertize in latest technology nodes in one of the below
domains or all of these.
1.Floor planning at Full chip level or Macro or Block Level a.Macro placement, power grid implementation, power routing, special routing like analog signals etc
b.Power collapse/Low power implementation flow
2.P&R: Place and route at chip level or block level, perform placement, timing closure in P&R mode, perform clock tree synthesis , routing etc
3.Timing closure/STA
a.Perform STA using primetime Si or Tempus or any industry standard STA engine, timing closure, ECO generation, timing correlation
b.Deep understanding of timing skills to perform correlation, timing fixes , corner/voltage definetions etc
4.Clock Tree Synthesis:
a.Perform custom or regular clock tree implementation at block level or top level.
b.Clock tree balance of complicated tree, clock power reduction
techniques etc
5.Low Power Implementation
a.Power collapse/power gaing techniques/implementation
b.UPF/CPF flow knowledge
c.CLP/FV
6. Physical Verification Using Calibre a.Running all the PV checks (DRc/LVS/ERC/Softcheck ) and deep understanding of all the rules and fixes
7. Perl/Python/Shell script experience is also preferred to help with automation
All your information will be kept confidential according to EEO guidelines.
Skills Required
- Floorplanning at full-chip, block, or macro level including macro placement and power grid implementation
- Place and route (P&R) at chip or block level including placement, timing closure in P&R mode, routing
- Timing closure and Static Timing Analysis (STA) using PrimeTime Si, Tempus or equivalent STA engines
- Clock Tree Synthesis (CTS) including complex tree balancing and clock power reduction techniques
- Low-power implementation including power collapse techniques and UPF/CPF flow knowledge
- Physical verification using Calibre (DRC/LVS/ERC/Softchecks) and rule-fix understanding
- Ability to take hardmacros from netlist through P&R to GDS including timing closure, formal and physical verification
- Experience with EDA physical design tools (examples: Cadence Innovus, Synopsys ICC2, PrimeTime Si, Calibre, Tempus)
- Perl, Python or Shell scripting for automation
What We Do
Mirafra Technologies, is a technology consulting company with focus on semiconductor Design Services, Embedded Software Development and Digital Transformation. Mirafra has a strong team of more than a 1000 engineers. We are headquartered in Bangalore with offices at Hyderabad, Chennai & Pune. We have offices in US and currently have 30 people working across North America. We also have operations in Singapore and Sweden. Mirafra engineers have delivered hundreds of successful projects and have repeatedly demonstrated an ability to solve the toughest problems. We invest in hiring the best engineers and then provide them with continuous training and development opportunities. Mirafra prides itself on having long and continuous engagements with its customers. We have more than 20 engagements which have been going on for more than 4 years each, with 4 of them for more than 8 years. Our customers range from startups to the top 10 semiconductor companies
