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Design and specify hardware security architectures and requirements, perform attack modeling and pre-silicon vulnerability analysis, review RTL and firmware implementations, advise/train teams, support certification and evaluators, interface with customers and product teams, and perform root cause analysis of security defects.

Define and drive SoC hardware security architecture and requirements, including HSM, secure boot/Root of Trust, cryptographic IP, and secure key provisioning. Lead threat modeling, vulnerability analysis, and HW/SW co-design to embed security across RTL, DFT, physical design, and firmware. Ensure compliance with cybersecurity and functional safety standards, collaborate cross-functionally, and provide technical leadership for system-level security validation.

Manage the lifecycle and governance of IT security policies and maintain the policy library. Coordinate stakeholder reviews, ensure framework alignment, and produce clear policy communications. Plan, deploy, and measure targeted security trainings via LMS and microlearning; create supporting visuals and short videos. Track KPIs, support audits, triage policy requests, and continuously improve playbooks and workflows.

Characterize and model next-generation non-volatile memory (NVM) technologies, perform statistical reliability analysis, set qualification requirements, collaborate with foundries and product teams to ensure high-volume production reliability, and communicate results to internal and external stakeholders.

Design and deliver high-speed, high-linearity analog and SERDES circuit blocks for automotive transceivers, focusing on block-level ownership and silicon validation.

Design and verify DFT features at subsystem and top levels: insert and verify MBIST, analyze/fix scan DRCs, run ATPG coverage and pattern generation, insert TAP/IO/test pinmux, perform power-aware RTL/GLS simulations, and support pattern bring-up with product and test teams.

Lead development and execution of verification plans and testbenches for digital IP. Create UVM/OVM testbench components, constrained-random and directed tests, SVA assertions, functional coverage models, and apply formal methods. Debug RTL, analyze coverage results, mentor engineers, and collaborate with global SoC/IP teams to drive zero-defect quality and productivity improvements.

Lead verification for MCU/MPU digital IP: define and execute verification plans, build UVM-based testbenches and SVA, develop constrained-random and directed tests, apply formal methods, debug failures, analyze RTL and coverage, and mentor a small team to ensure zero-defect delivery.

Define roadmap and product specifications for protocol bridges and connectivity hubs. Engage customers, perform competitive analysis, coordinate cross-functional teams to develop demos, reference designs, and documentation. Provide application support, technical training, and contribute to standards while overseeing development of demonstration boards and securing design-ins.

Provide litigation support and manage complex e-discovery projects, administer litigation holds, handle subpoenas and legal notices, coordinate witnesses, depositions and trials, track claim matters, and collaborate with outside counsel using legal technology and Microsoft Office tools.