Top Tech Jobs & Startup Jobs

Drive GTM strategy for robotics and Edge AI in the Americas: identify use cases, secure design wins, enable partners and sales, influence product roadmaps, deliver market insights, and manage stakeholder relationships to grow revenue over a 3-5 year horizon.

Provide advanced technical leadership for system- and application-level design, integration, validation, and customer support of embedded and connected systems. Develop reference designs, troubleshoot hardware/software issues, enable customers with training and documentation, support product launches, and mentor junior engineers while collaborating with product, hardware, software, and sales teams.

Design and implement cost-effective test methods for IP on advanced-node SOC microprocessors. Support characterization, qualification, production test, and debug; develop diagnostic programs; collaborate with design and verification teams pre-tapeout; understand high-speed ATE hardware and semiconductor manufacturing test economics.

Lead export control and sanctions compliance for the AMEC region, driving strategy implementation, regulatory adherence, and operational efficiency while engaging stakeholders and optimizing processes.

Develop and execute IP verification plans using SystemVerilog/UVM and SVA. Create random and directed tests, implement monitors/drivers/checkers, debug failures, collect/analyze coverage, and perform assertion-based formal verification. Maintain verification environments, scripts, and Makefiles while collaborating with architecture, design, and verification teams to ensure IP quality.

Design and verify DFT features at subsystem and top levels: insert and verify MBIST, analyze/fix scan DRCs, run ATPG coverage and pattern generation, insert TAP/IO/test pinmux, perform power-aware RTL/GLS simulations, and support pattern bring-up with product and test teams.

Design and deliver digital IP (RTL) for SoC components using Verilog/SystemVerilog; plan documentation and schedules; collaborate with verification to achieve full coverage; perform quality checks (Lint, CDC, STA); track metrics and support SoC integration, validation, and field issue resolution.

Lead development and execution of verification plans and testbenches for digital IP. Create UVM/OVM testbench components, constrained-random and directed tests, SVA assertions, functional coverage models, and apply formal methods. Debug RTL, analyze coverage results, mentor engineers, and collaborate with global SoC/IP teams to drive zero-defect quality and productivity improvements.

Lead development and execution of verification plans and testbenches for MCU/MPU digital IP. Build UVM/OVM components, constrained-random stimulus, SVA assertions, formal checks, coverage models, and debug failures. Provide technical leadership, mentor engineers, and collaborate with global SoC/IP teams to drive best practices.

Lead verification for MCU/MPU digital IP: define and execute verification plans, build UVM-based testbenches and SVA, develop constrained-random and directed tests, apply formal methods, debug failures, analyze RTL and coverage, and mentor a small team to ensure zero-defect delivery.