DFT Engineer
You will join a team working on leading-edge projects in the Business Unit (BU) MCU & MPU Engineering & Design Enablement (MMEDE). MMEDE BU brings the technology and ecosystem relationships for next gen automotive Processing, Edge Processing & Radar Processing products.
Your Responsibilities:
Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.
Inserting of MBIST RTL for memories & Verifying them.
Analyzing Scan DRCs & fixing them in RTL.
Analyzing ATPG reports on coverage & devise mechanism to improve coverage & generating patterns for ATE.
Inserting of TAP, IOs, Test Pinmux using NXP DFT flows.
Power Aware RTL/ GLS simulation bringup & taking care of the regression suite for both Non-ATPG & ATPG simulations.
Bringing up Patterns on Wafer probe & on Final Test by working closely with Product & Test teams.
Your Profile:
DFT engineer with 5+ years of experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
Self-driven, results-oriented with a positive outlook, and a clear focus on high quality deliverables.
Empathic communicator, able to see things from the other person's point of view.
Should be willing to take up new challenges in the project and be a team player.
The engineer should be well versed in Digital Design Concept, preferably having subject knowledge on Verilog/VHDL RTL coding.
The candidate should preferably have experience in any one of the following areas.
Scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
Able to debug and root cause problems in simulation failures.
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
#LI-6692Skills Required
- 5+ years experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, and ATPG.
- Well versed in Digital Design concepts.
- Experience inserting MBIST RTL for memories and verifying them.
- Analyze Scan DRCs and fix issues in RTL.
- Analyze ATPG coverage reports, improve coverage, and generate patterns for ATE.
- Experience with TAP, IO insertion and Test Pinmux using NXP DFT flows.
- Power-aware RTL and gate-level simulation (GLS) bring-up and maintaining regression suites for ATPG and non-ATPG simulations.
- Able to debug and root-cause simulation failures, including timing/SDF issues.
- Verilog and/or VHDL RTL coding knowledge.
- Experience with scan insertion, ATPG DRC and coverage analysis, and simulation debug (timing/SDF).
What We Do
NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA
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