Top Tech Jobs & Startup Jobs

Lead and coordinate HR M&A activities including due diligence data collection, project planning, cross-functional meetings, Day 1 readiness, vendor coordination, change communications, and integration tasks with HR COEs to ensure timely, compliant, employee-focused integrations.

Design and deliver executive‑level presentations by translating complex technical, financial, and strategic content into clear visual narratives. Create templates, maintain brand standards, manage multiple high-priority projects under tight timelines, advise senior stakeholders, and collaborate with marketing, product, finance, and communications teams. Maintain presentation assets, ensure accuracy and confidentiality, and present design recommendations to leadership.

The role involves designing AI systems for IC calibration and optimization, collaborating with design teams, and applying ML techniques to analog/mixed-signal circuits.

Manage end-to-end execution of Central CAD & Design Services programs: planning, schedules, risk tracking, stakeholder cadence, CAD/EDA readiness, communications, dashboards, JIRA/Confluence/SharePoint operations, and process improvements leveraging productivity and enterprise AI tools to scale program management.

Design and implement functional verification environments for multi-core SoCs using SystemVerilog/UVM. Develop test plans, random and directed tests, coverage-driven verification, reference models, BFMs, and scripts; debug failures with designers; verify boot code and build scalable verification tools and regression infrastructure.

Lead test engineering for NPI: define test plans, design ATE hardware, implement production and characterization test programs, perform silicon bring-up, and optimize test time and yield. Collaborate with product engineering, QA, program management, and operations using ATE platforms and test instruments.

Senior individual contributor owning IP release qualification for SoC subsystems: enforce RTL static quality (lint/CDC/RDC), validate synthesis readiness (SDC/UPF), ensure DFT/test readiness, manage IP delivery checklists and packaging, triage integration issues with SoC teams and vendors, and drive cross-functional alignment and automation to meet production-quality schedules.

Design and own core Python-based verification infrastructure: declarative build graph, run-record store, simulator backends, failure bundles, CI/grid integrations, and operational deployment; support AI agents with deterministic guardrails and provide docs and rollout support to DV teams.

Lead the SOC design team, manage high-quality SOC designs, integrate IPs, and ensure successful product execution through collaboration and technical leadership.

Design, implement, verify, and document micro-architecture and RTL for complex power-management ASICs. Own end-to-end development from architecture and RTL coding to synthesis, timing closure, formal and gate-level verification, silicon bring-up, documentation, and cross-functional reviews while improving design and verification methodologies.