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The intern will support the data science team by gathering data, performing exploratory analysis, building machine learning models, and developing visualizations to aid business insights.

As a Principal Test Engineer, you'll develop and manage ATE test programs, collaborate with design teams, and drive test cost reduction and yield improvement for semiconductor chips production.

Lead FP&A for the Data Center Switch business unit: budgeting, forecasting, variance analysis, product P&Ls, margin and opex analysis, cross-functional partnering, executive reporting, annual/quarterly planning, strategic initiatives (M&A, ROI, long-range planning), and manage and mentor an FP&A team.

Lead the development and verification of SoC emulation models, optimize performance, automate flows, and collaborate with design teams.

We are seeking a Timing/STA Engineer with expertise in timing constraints development and STA methodologies for intricate SoC designs. Responsibilities include developing timing constraints, conducting static timing analysis, automating STA processes, and collaborating with cross-functional teams for design optimization.

Support Marvell's global export compliance program with product, software, and technology classification under U.S. and international export and customs regulations. Manage visitor and deemed export processes, support trade due diligence, maintain SOPs and training, prepare classification requests and license applications, and collaborate with engineering, operations, and global teams on compliance projects.

The role involves improving demand forecast accuracy, implementing ML models, and collaborating with various teams to analyze market trends.

The role involves leading SerDes IP integration, coordinating engineering resources, diagnosing signal integrity issues, and supporting high-speed interface applications, while managing customer technical escalations and providing documentation and presentations.

Lead advanced packaging technology roadmap and development for high-performance AI/HPC and networking products. Define package architecture, chiplet topology, PDN and thermal strategies; run signal/power integrity and EM simulations; partner with silicon teams, OSATs and foundries; drive manufacturability, qualification, and volume readiness while creating IP and proof-of-concept technologies.

The Staff Engineer for Lab Operations will oversee all aspects of the Santa Clara hardware lab, including equipment management, vendor relationships, lab organization, and logistics for customer demos and tradeshows.