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Reposted 18 Days AgoSaved
In-Office
Westlake Village, CA, USA
168K-248K
Senior level
168K-248K
Senior level
Semiconductor
The engineer will design and validate high-speed RF and Analog circuits for optical communication, ensuring industry-leading performance in TIAs and other components.
Top Skills: AnalogBicmosEda Cad ToolsRfSigeTia
Reposted 18 Days AgoSaved
In-Office
Santa Clara, CA, USA
105K-158K
Mid level
105K-158K
Mid level
Semiconductor
Develop and innovate embedded network software for Teralynx products, covering all software development phases from requirements to testing.
Top Skills: C,C++,Python,Linux
Reposted 19 Days AgoSaved
In-Office
Santa Clara, CA, USA
124K-186K
Senior level
124K-186K
Senior level
Semiconductor
Develop verification environments and testbench components for ASIC/SOC designs using SystemVerilog, C, and Python. Collaborate with designers and debug issues.
Top Skills: CC++PythonSystemverilogUvmVerilog
Reposted 19 Days AgoSaved
In-Office
Santa Clara, CA, USA
176K-264K
Expert/Leader
176K-264K
Expert/Leader
Semiconductor
Lead and grow a technical support team, manage customer engagements, foster relationships, and contribute to global leadership projects related to data center and AI infrastructure.
Top Skills: Computer EngineeringComputer ScienceNetworking ProtocolsSaiSonicSwitch Driver DevelopmentVlsi Design
Reposted 19 Days AgoSaved
In-Office
Westborough, MA, USA
177K-261K
Senior level
177K-261K
Senior level
Semiconductor
Lead and mentor a team of engineers in physical design and project management while ensuring successful ASIC development and stakeholder communication.
Top Skills: AsicClock Tree SynthesisFloor PlanningGdsPhysical VerificationPlace And RouteRtlSocTiming Closure
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Reposted 19 Days AgoSaved
In-Office
Santa Clara, CA, USA
124K-186K
Senior level
124K-186K
Senior level
Semiconductor
The engineer will perform static timing analysis, drive timing closure of ASIC designs, collaborate with teams, and improve design methodologies.
Top Skills: Cadence TempusEda ToolsPerlPrimetime SiPythonSynopsys PrimetimeTcl
Reposted 19 Days AgoSaved
In-Office
Santa Clara, CA, USA
131K-196K
Senior level
131K-196K
Senior level
Semiconductor
Lead mechanical and thermal integration for fiber optic designs, create 3D models, and collaborate with cross-functional teams on optical solutions.
Top Skills: Allegro Pcb ViewerAnsysAutocadFlothermKlayoutPro-ESolidworks
Reposted 19 Days AgoSaved
In-Office
Santa Clara, CA, USA
131K-196K
Mid level
131K-196K
Mid level
Semiconductor
Lead the design and development of hardware platforms for optical transceivers, managing the product lifecycle and collaborating with cross-functional teams to ensure performance compliance.
Top Skills: AdsC++Cadence VirtuosoClarity 3DCommunications ProtocolsEmbedded FirmwareHfssI2CI3CMatlabPowerdcPowersiPythonSchematic CaptureSilicon PhotonicsSpiSpmiUart
Reposted 19 Days AgoSaved
In-Office
Santa Clara, CA, USA
190K-285K
Senior level
190K-285K
Senior level
Semiconductor
Design and verify mixed signal ICs including ADCs and PLLs. Collaborate with cross-functional teams and conduct lab testing for prototypes.
Top Skills: AdcCmosDacHsimMatlabPllSpectreSpiceVerilog
Reposted 19 Days AgoSaved
In-Office
Santa Clara, CA, USA
23-47
Internship
23-47
Internship
Semiconductor
The role involves developing semiconductor packages, engaging in design and layout reviews, and supporting new product introductions while studying for a PhD.
Top Skills: ApdSemiconductor TechnologySubstrate Fabrication
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