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Reposted 9 Days AgoSaved
In-Office
2 Locations
184K-273K Annually
Expert/Leader
184K-273K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
Lead implementation of DFT/Test for complex ASIC/SoC and chiplet designs using Tessent and related EDA tools. Define DFT architecture, run insertion flows, generate patterns, support STA constraints, and drive post-silicon bring-up and debug. Mentor a small DFT team and enhance methodologies and tools across multi-die custom compute designs.
Top Skills: 2.5D3D IcC-ShellChiplet DftDesign Compiler (Dc)GenusIclIeee 1687Ip-DfxMbistModusNc-SimPdlPerlPost-Silicon Bring-UpPtapPythonScanSpyglassStaStapTclTessentTessent SsnTmax
Reposted 9 Days AgoSaved
In-Office
2 Locations
129K-191K Annually
Senior level
129K-191K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Responsible for high-performance hardware design of coherent DSPs, including simulation, testing, and collaboration with various engineering teams for board validation and bring-up.
Top Skills: AdsAltiumAnsys HfssEthernetFpgaOrcad Cis/CipPam4PspiceSerdesSiwaveTdr ScopesVnaΜcontrollerΜprocessor
Reposted 9 Days AgoSaved
In-Office
Santa Clara, CA, USA
143K-215K Annually
Senior level
143K-215K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The Principal Hardware Engineer will design, develop, and test electrical hardware for optical modules, mentor junior engineers, and collaborate with teams for hardware specifications while ensuring effective troubleshooting and validation of components.
Top Skills: AllegroCad ToolsElectrical Hardware DesignFirmwareOrcadPcb LayoutSemiconductor Processing
Reposted 9 Days AgoSaved
In-Office
Santa Clara, CA, USA
147K-220K Annually
Senior level
147K-220K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Lead the micro-architecture and RTL development for advanced SoC designs, ensuring functional correctness and integration across multiple systems while collaborating with various engineering teams.
Top Skills: CxlD2D ProtocolsDdrPciePerlPythonRtl LintingSoc ArchitectureSpyglassVerilogVhdl
Reposted 9 Days AgoSaved
In-Office
Santa Clara, CA, USA
121K-182K Annually
Mid level
121K-182K Annually
Mid level
Artificial Intelligence • Automotive • Semiconductor
Design PCB hardware for various projects including chip test infrastructure, focusing on simulation, testing, component selection, and board-level diagnostics.
Top Skills: Cadence AllegroOrcad CapturePcbPythonVerilog
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Reposted 9 Days AgoSaved
In-Office
Santa Clara, CA, USA
224K-336K Annually
Expert/Leader
224K-336K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
As a Senior Distinguished Engineer, lead the architecture of high-performance networking ASICs, foster innovation, and mentor engineers. Collaborate with cross-functional teams to enhance scalable data infrastructures for AI and cloud applications.
Top Skills: Asic ArchitectureChiplet MethodologiesCommunication ProtocolsHigh-Performance NetworkingSilicon DesignSystem-Level Architecture
Reposted 9 Days AgoSaved
In-Office
Santa Clara, CA, USA
159K-238K Annually
Senior level
159K-238K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
As a Design Verification Engineer, you will verify chip designs, develop test plans, and lead teams on verification projects, ensuring high-speed data transfer meets specifications.
Top Skills: Arm AssemblyC++Eda Verification ToolsLinuxPerlPythonSystem VerilogUvm
155K-232K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Responsible for designing, implementing, and maintaining firmware for high-speed interconnects, ensuring reliable data transfer across complex hardware systems, and developing firmware APIs for resource management.
Top Skills: Arm Cortex-MCC++Esp32GitIn-Circuit DebuggersJtagRisc-VSwd
Reposted 9 Days AgoSaved
In-Office
Westlake Village, CA, USA
120K-178K Annually
Mid level
120K-178K Annually
Mid level
Artificial Intelligence • Automotive • Semiconductor
The role involves the design and validation of high-speed analog circuits, particularly transimpedance amplifiers for optical data communication. Responsibilities include active circuit design, working on millimeter wave structures, and collaborating on post-silicon validation and production transition.
Top Skills: Eda Cad ToolsFinfet CmosSige Bicmos
Reposted 9 Days AgoSaved
In-Office
Santa Clara, CA, USA
134K-201K Annually
Senior level
134K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Lead development of SoC emulation models, conduct validation, debug complex issues, optimize performance, and collaborate with teams while utilizing various platforms and scripting languages.
Top Skills: Arm AssemblyC++CadencePalladiumPerlPythonShellSiemensSynopsysSystemverilogTclUvmVeloceZebu
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