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The Senior Director of Product Line Management will drive product strategy and design wins for silicon photonics solutions, collaborating across teams to ensure market success.

Develop firmware for CXL and PCIe devices, lead projects and mentor team members, collaborate across functions, and contribute to project planning.

The SoC/RTL Low-Power Expert will manage power architecture, enforce low-power design practices, drive RTL estimation, and supervise other engineers while ensuring power behavior accuracy throughout the silicon lifecycle.

Lead test strategy and architecture for wafer- and die-level silicon photonics testing. Design automated, high-throughput optical testbeds integrating lasers, OSAs, RF instruments, and precision alignment. Collaborate on DFT/DFM, perform electro-optic characterization (insertion loss, PDL, S-parameters, BER), develop data analysis/SPC pipelines to optimize yield, and coordinate with foundries, OSATs, and test-vendor partners.

Develop and maintain UVM testbenches and verification collateral for complex SoC architectures. Create test plans and strategies, develop tests to meet coverage goals, debug failures, and collaborate with designers to resolve issues. Support verification environments and regression/bug-tracking workflows.

Design and implement synthesizable RTL (Verilog/SystemVerilog) for digital IP and subsystems. Perform linting, CDC and low-power checks, analyze timing/area/power tradeoffs, support synthesis and timing closure with physical design, debug via simulation/emulation/FPGA/silicon, participate in silicon validation, and mentor junior engineers.

SoC-level design verification engineer responsible for developing and maintaining UVM testbenches, creating test plans and coverage-driven tests, building verification environments, debugging failures, and working with designers to resolve issues. Requires RTL verification skills and scripting for automation and test infrastructure.

Design and implement UVM testbench components and verification collateral; develop test plans, constrained-random tests, and coverage metrics; run simulations, debug failures with designers, and contribute automation and AI-enhanced verification tools while mentoring junior engineers.

SoC-level design verification engineer responsible for developing and maintaining UVM testbenches, creating verification plans and tests to meet coverage goals, debugging failures with designers, and mentoring junior engineers. Works with verification tools, bug tracking, regression mechanisms, and uses C/C++ and scripting for automation on Linux.

Lead SoC-level design verification: create test plans, build and maintain UVM testbenches, develop tests to meet coverage goals, debug failures with designers, and mentor junior engineers.