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The Senior Principal Engineer will lead the end-to-end development of a photonic chiplet, integrating electrical and photonic circuits, and ensuring robust system validation through cross-functional collaboration.

The Principal Test Engineer will lead development of ATE test solutions, innovate high-speed testing hardware, craft test plans, and optimize test flows while collaborating with cross-functional teams.

The Principal Engineer will architect simulation test benches, develop and execute test plans, debug failures, and mentor junior engineers in verifying chip designs.

Oversee the strategy and management of health and welfare programs for the Americas, ensuring compliance and alignment with global objectives. Lead benefits program implementations, manage vendor relationships, and enhance employee communication about benefits.

The Hardware Design Principal Engineer will develop high-performance board-level hardware solutions, leading efforts in design, testing, and customer interactions across various networking and storage applications.

The Principal Engineer will lead DFT architecture on multi-die designs, mentor engineers, and implement DFT methodologies for complex ICs.

The role involves planning, designing, and verifying digital circuits in SerDes IP, coordinating with cross-functional teams to deliver high-speed communication solutions.

This role involves physical design of complex chips, integrating designs across disciplines, mentoring juniors, and scripting for automation.

The Senior Director Systems Architect will lead high-speed connectivity architecture, engage with tier-1 customers, and influence product roadmaps and design strategies.

Support customers integrating Marvell Ethernet PHYs through schematic review, board bring-up and debugging, lab/field trials, troubleshooting, technical training, sales support, cross-functional collaboration, and creation of application notes and technical collateral.