Top Tech Jobs & Startup Jobs

The Rack Level Integration Engineer will validate and integrate components within AI compute racks, leading design and implementation for performance and reliability.

The Principal Application Engineer will lead technical projects, resolve complex issues, and interface with key customers to enhance product deployment in AI and data center platforms, utilizing expertise in hardware systems and DSP technologies.

Lead the strategy and transformation of FP&A systems at Marvell, focusing on AI integration, modernization of technology stacks, and driving business-critical initiatives.

The Demand Planner is responsible for improving forecast accuracy, analyzing market trends, and collaborating across functions to support supply chain effectiveness and strategic decision-making.

The Senior Director of Product Line Management will drive product strategy and design wins for silicon photonics solutions, collaborating across teams to ensure market success.

Develop firmware for CXL and PCIe devices, lead projects and mentor team members, collaborate across functions, and contribute to project planning.

The SoC/RTL Low-Power Expert will manage power architecture, enforce low-power design practices, drive RTL estimation, and supervise other engineers while ensuring power behavior accuracy throughout the silicon lifecycle.

Lead test strategy and architecture for wafer- and die-level silicon photonics testing. Design automated, high-throughput optical testbeds integrating lasers, OSAs, RF instruments, and precision alignment. Collaborate on DFT/DFM, perform electro-optic characterization (insertion loss, PDL, S-parameters, BER), develop data analysis/SPC pipelines to optimize yield, and coordinate with foundries, OSATs, and test-vendor partners.

Develop and maintain UVM testbenches and verification collateral for complex SoC architectures. Create test plans and strategies, develop tests to meet coverage goals, debug failures, and collaborate with designers to resolve issues. Support verification environments and regression/bug-tracking workflows.

Design and implement synthesizable RTL (Verilog/SystemVerilog) for digital IP and subsystems. Perform linting, CDC and low-power checks, analyze timing/area/power tradeoffs, support synthesis and timing closure with physical design, debug via simulation/emulation/FPGA/silicon, participate in silicon validation, and mentor junior engineers.