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Reposted 3 Months AgoSaved
In-Office
San Jose, CA, USA
Expert/Leader
Expert/Leader
Artificial Intelligence • Hardware • Software
Lead system-level reliability for Etched's servers, racks, and datacenter platforms. Define reliability strategy, qualification gates, accelerated and environmental testing, failure analysis, and reliability modeling (MTBF, Weibull, FIT). Build telemetry, fleet feedback, and validation processes; drive cross-functional root-cause investigations; enforce ODM/JDM reliability commitments; and hire and lead a product reliability engineering organization to ensure enterprise-grade field reliability.
Top Skills: Accelerator/Gpu SystemsAi AcceleratorAltAstDvtEnvironmental TestingEvtFit Rate AnalysisFleet TelemetryFmeaHaltHassHigh-Density Power DeliveryLiquid CoolingMtbfNpiOdm/JdmPower CyclingPvtServer And Rack-Scale InfrastructureShock TestingTelemetry Analysis PipelinesThermal CyclingVibration TestingWeibull AnalysisWeibull Lifetime Modeling
Reposted 3 Months AgoSaved
In-Office
San Jose, CA, USA
200K-265K Annually
Senior level
200K-265K Annually
Senior level
Artificial Intelligence • Hardware • Software
Design and optimize AI accelerator architectures focusing on performance and efficiency for transformer workloads. Collaborate cross-functionally on innovative chip designs.
Top Skills: C/C++Gem5PythonRustSystemcSystemverilogVerilog
Reposted 3 Months AgoSaved
In-Office
San Jose, CA, USA
110K-250K Annually
Senior level
110K-250K Annually
Senior level
Artificial Intelligence • Hardware • Software
The Technical Recruiter will manage the full-cycle recruiting process for technical talent, partner with hiring managers, source candidates creatively, and enhance recruiting workflows.
Top Skills: AIRecruiting SoftwareTechnical Sourcing Tools
Reposted 3 Months AgoSaved
In-Office
San Jose, CA, USA
175K-400K Annually
Mid level
175K-400K Annually
Mid level
Artificial Intelligence • Hardware • Software
You will port models to new architectures, optimize runtime and communication layers, and develop performance profiling tools for inference operations.
Top Skills: C++InfinibandJaxKubeflowKubernetesLinuxNvlinkPyTorchRayRustSlurm
Reposted 3 Months AgoSaved
In-Office
San Jose, CA, USA
150K-350K Annually
Senior level
150K-350K Annually
Senior level
Artificial Intelligence • Hardware • Software
Ensure first silicon delivery for ASICs, develop test benches, and possess experience in hardware verification and scripting languages.
Top Skills: Hbm3PythonSystem VerilogVerilator
Reposted 3 Months AgoSaved
In-Office
San Jose, CA, USA
200K-375K Annually
Mid level
200K-375K Annually
Mid level
Artificial Intelligence • Hardware • Software
The Physical Design Engineer will oversee physical design implementations, optimize CAD infrastructures, and drive project convergence through dashboards, focusing on design methodologies and flows from RTL to GDSII.
Top Skills: Eda ToolsGdsiiOpenroadPhysical DesignPythonRtl SynthesisUpf
Reposted 3 Months AgoSaved
In-Office
San Jose, CA, USA
150K-350K Annually
Senior level
150K-350K Annually
Senior level
Artificial Intelligence • Hardware • Software
The Senior Layout PCB Engineer will design and optimize PCBs for high-speed applications, focusing on signaling, power distribution, and complex HDI stack-ups, while collaborating with teams to enhance performance and manufacturability.
Top Skills: Cadence Allegro Pcb Design Tools
Reposted 3 Months AgoSaved
In-Office
San Jose, CA, USA
Senior level
Senior level
Artificial Intelligence • Hardware • Software
Lead formal verification for complex ASIC IP and SoC subsystems. Define strategy, write SVA properties, build reusable formal environments, drive proof convergence, debug RTL/protocol bugs with formal counterexamples, and collaborate with architects, RTL, UVM DV, emulation, software, and firmware teams toward formal sign-off.
Top Skills: AsicAxi/AmbaCadence JaspergoldDmaEthernetNocPciePerlPythonRtlSiemens Questa FormalSynopsys Vc FormalSystemverilogSystemverilog Assertions (Sva)TclUvm
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