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Develop performance models for AI chips, analyze deep learning workloads, optimize hardware-software co-design, and collaborate on architectural decisions for efficiency.

The Head of Lab Operations will manage lab operations, oversee team supervision, coordinate hardware validation, and maintain lab infrastructure.

The DFT Engineer ensures efficient testability of ICs, develops DFT architectures, verifies implementations, and collaborates with teams for optimal production support.

Design and optimize AI accelerator architectures focusing on performance and efficiency for transformer workloads. Collaborate cross-functionally on innovative chip designs.

The Core Operations role involves leading strategic initiatives, facilitating leadership decision-making, driving collaboration, and establishing operational metrics to enhance business performance.

The engineer will design complex IC substrate layouts, focusing on power delivery and high-speed signal integrity for high-performance AI processors. Responsibilities include collaborating with teams for design feasibility and conducting design validation.

You will port models to new architectures, optimize runtime and communication layers, and develop performance profiling tools for inference operations.

The RTL Design Engineer will develop design verification strategies for ASIC designs, ensuring efficiency and performance of AI chips.

The Pod Software Engineer develops and optimizes networking solutions for large-scale inference workloads, focusing on RDMA-based communication and performance telemetry within multi-rack clusters.

The Technical Recruiter will manage the full-cycle recruiting process for technical talent, partner with hiring managers, source candidates creatively, and enhance recruiting workflows.