Top Tech Jobs & Startup Jobs

Designs complex IC substrate packages for high-power AI processors and accelerators, including large multilayer layouts, dense routing, power delivery networks, and signaling beyond 50GHz. The role optimizes CoWoS interposer designs, performs DRC and LVS verification, collaborates with silicon, SI/PI, packaging, and manufacturing teams, and supports design reviews and technical guidance for junior engineers.

Manage and maintain Allegro schematic symbol and PCB footprint libraries. Create, validate, and organize accurate, manufacturable ECAD components; maintain metadata, part numbering, approvals, and datasheet links. Collaborate with electrical, layout, manufacturing, and supplier teams to resolve library issues, meet IPC, JEDEC, and DFM requirements, and improve fabrication yield. Perform quality checks and use version control and SKILL scripting to preserve data integrity and automate library tasks.

Own block- and subsystem-level physical design from RTL synthesis through GDSII sign-off. Perform floorplanning, placement, CTS, routing, timing closure, sign-off (EM/IR/RC/DRC/LVS), generate abstracts for hierarchical integration, improve PPA with RTL collaboration, and supervise third-party delivery.

Lead external financial reporting and equity accounting, including stock-based compensation, EPS/dilution, SEC filings (10-Q/10-K), XBRL tagging, auditor coordination, SOX controls, and selection/implementation of reporting systems to build scalable reporting infrastructure.

Design and validate power delivery networks for high-current ASIC systems: perform PDN pre/post-layout analysis, DC IR-drop and AC impedance simulations, VRM modeling, thermal co-simulation, DRC/PI checks, bring-up debug, and maintain simulation-to-hardware correlation.

The Physical Design Engineer will focus on block-level implementation, timing closure, PPA optimization, and supervising outsourced design work while improving design flows.

The Technical Program Manager will oversee program delivery, align teams, manage vendor relationships, and optimize processes in the Infrastructure organization.

As a Design Verification Engineer, you will create and maintain UVM/SystemVerilog testbenches, execute verification plans, debug issues, and collaborate with cross-functional teams to ensure IP functionality and performance.

The Design Verification Engineer will lead IP subsystem verification, develop UVM/SystemVerilog environments, and collaborate with cross-functional teams to validate hardware-software performance.

As a Design Verification Engineer, you will collaborate with architects and RTL designers to verify designs, develop test plans and infrastructure, ensure performance, and debug issues across the hardware-software stack.