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As a Design Verification Engineer, you will create and maintain UVM/SystemVerilog testbenches, execute verification plans, debug issues, and collaborate with cross-functional teams to ensure IP functionality and performance.

The Design Verification Engineer will lead IP subsystem verification, develop UVM/SystemVerilog environments, and collaborate with cross-functional teams to validate hardware-software performance.

As a Design Verification Engineer, you will collaborate with architects and RTL designers to verify designs, develop test plans and infrastructure, ensure performance, and debug issues across the hardware-software stack.

The Electrical Engineer will lead schematic design for accelerator modules, collaborate on system requirements, and manage documentation and testing for hardware systems.

The internship involves hands-on product design, development of design infrastructure, and system integration for high power ASIC systems, focusing on mechanical and electrical engineering aspects.

The Emulation Engineer will oversee SoC bring-up and debugging, develop automated flows for pre-silicon validation, implement hybrid emulation environments, and create chip-to-chip network models, collaborating with various teams.

Build and maintain automation, CI/CD, and observability for hybrid cloud and on-prem HPC workflows. Optimize Slurm scheduling, manage containerized environments, integrate cloud resources, implement caching/artifact systems, and support security, secrets management, and developer productivity across hardware and software teams.

As a DFT Intern, you will refine DFT flow automation, support chip-level regression, and aid DFT verification, working closely with design teams.

Lead definition of system-level performance metrics and abstractions across custom silicon, runtimes, compilers, and distributed inference clusters. Design telemetry taxonomies, cross-layer event correlation, time-alignment strategies, and cluster-scale performance reasoning. Build developer tooling and analysis engines to surface actionable insights and influence instrumentation for future hardware.

Own end-to-end product economics across semiconductor and system costs, manufacturing, supply, inventory, pricing, customer monetization, and margins. Build financial models, product-roadmap business cases, forecasts, dashboards, and investment analyses. Partner with Product, Engineering, Manufacturing, Supply Chain, GTM, and Finance to improve margins, guide capital allocation, and translate AI infrastructure performance into pricing and executive decisions.