Top Tech Jobs & Startup Jobs

Lead definition of system-level performance metrics and abstractions across custom silicon, runtimes, compilers, and distributed inference clusters. Design telemetry taxonomies, cross-layer event correlation, time-alignment strategies, and cluster-scale performance reasoning. Build developer tooling and analysis engines to surface actionable insights and influence instrumentation for future hardware.

Own end-to-end product economics across semiconductor and system costs, manufacturing, supply, inventory, pricing, customer monetization, and margins. Build financial models, product-roadmap business cases, forecasts, dashboards, and investment analyses. Partner with Product, Engineering, Manufacturing, Supply Chain, GTM, and Finance to improve margins, guide capital allocation, and translate AI infrastructure performance into pricing and executive decisions.

Research and write technically rigorous content about AI, inference, compute, chips, systems, and infrastructure. Responsibilities include long-form analysis, product launches, leadership ghostwriting, customer case studies, technical briefs, social content, and data-driven visuals. The role partners closely with engineers and executives to develop original viewpoints, explain complex concepts, and establish Etched’s technical voice across audiences and channels.

Develop, deploy, and operate agentic AI systems that drive manufacturing decisions across S&OP, material planning, production, quality, logistics, and customer deployments. Embed with cross-functional teams to model demand, supply, BOMs, capacity, and risk; build agents that generate executable plans, propagate design changes, run historical replays and live evals, and continuously evaluate frontier models and optimization methods to improve ramp speed and schedule attainment.

Build AI systems that autonomously turn new model architectures into verified, production-ready kernels optimized for Etched hardware. Develop agentic tooling to generate, compile, profile, and iterate on implementations; design evals for correctness, stability, latency, and efficiency; turn profiler traces and hardware signals into learnable datasets; ship model-generated improvements and partner with architecture teams to influence hardware-software roadmap.

Own and architect the automated RTL-to-GDSII physical design flow: build/maintain CAD infrastructure, automate regressions and run management, integrate signoff tools, create PG meshes and DRC-clean floorplans, drive PPA tuning and timing correlation, and partner with block owners to encode methodology fixes for scalable tapeout.

Lead full-chip physical implementation from synthesis to GDSII: floorplanning, P&R, clocking, MMMC timing closure, timing constraints and ECOs, full-chip physical verification (DRC/LVS/ERC/antenna/density/fill), debug PV violations, and tapeout signoff using automated flows and Innovus.

Own block- and subsystem-level physical design from synthesis through GDSII sign-off: floorplanning, synthesis, placement, CTS, routing, timing closure, signoff (EM/IR/RC/DRC/LVS), generate abstracts and timing budgets, collaborate with RTL designers, and supervise outsourced PD work.

Lead end-to-end manufacturing test program management from prototype through mass production. Define test strategy, coordinate cross-functional teams, deploy test hardware/software/fixtures with CM/FATP partners, drive yield improvements and failure analysis, and travel to manufacturing sites to ensure production readiness.

The Global Supply Manager will strategically source and manage suppliers for L11 hardware, collaborating with engineering and operations to ensure efficient production and supply chain resilience.