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Design and optimize AI accelerator architectures focusing on performance and efficiency for transformer workloads. Collaborate cross-functionally on innovative chip designs.

You will port models to new architectures, optimize runtime and communication layers, and develop performance profiling tools for inference operations.

The Technical Recruiter will manage the full-cycle recruiting process for technical talent, partner with hiring managers, source candidates creatively, and enhance recruiting workflows.

Lead the development of system software for AI chips, manage software engineers, ensure high-performance ML platforms, and foster team growth.

Ensure first silicon delivery for ASICs, develop test benches, and possess experience in hardware verification and scripting languages.

The Physical Design Engineer will oversee physical design implementations, optimize CAD infrastructures, and drive project convergence through dashboards, focusing on design methodologies and flows from RTL to GDSII.

The Senior Layout PCB Engineer will design and optimize PCBs for high-speed applications, focusing on signaling, power distribution, and complex HDI stack-ups, while collaborating with teams to enhance performance and manufacturability.

Build critical infrastructure and custom applications, collaborate cross-functionally, and address operational challenges with a strong focus on delivering production-level code rapidly.

Work with package, PCB, ASIC, and system engineers to analyze high-speed interfaces (PCIe, Ethernet, SerDes), extract and validate S-parameter models, build HFSS 3D EM models, correlate simulation with lab measurements, and recommend design improvements to improve signal and power integrity across accelerator platforms.

Lead formal verification for complex ASIC IP and SoC subsystems. Define strategy, write SVA properties, build reusable formal environments, drive proof convergence, debug RTL/protocol bugs with formal counterexamples, and collaborate with architects, RTL, UVM DV, emulation, software, and firmware teams toward formal sign-off.