Top Tech Jobs & Startup Jobs

Provides technical leadership for global semiconductor EDA/CAD compute and design-data-management environments. Owns Perforce Helix and IPLM methodologies, project and workspace configuration, Linux-based engineering infrastructure, automation, legacy-data migration, documentation, training, and expert support. Develops Python and shell utilities, improves CAD workflow scalability, and partners with engineering and IT teams on infrastructure strategy, standardization, and adoption across analog and digital semiconductor design projects.

Provides technical leadership for global semiconductor engineering compute and CAD environments. Owns Perforce Helix and Methodics IPLM design-data-management methodologies, project and workspace configuration, Linux infrastructure, automation, legacy data migration, documentation, training, and escalation support. Develops Python and shell utilities, standardizes EDA workflows, supports Cadence environments, and collaborates with engineering and IT teams to create scalable, reliable infrastructure for analog and digital semiconductor design.

Design and integrate low-power digital RTL for mixed-signal semiconductor products from architecture through mass production. Responsibilities include Verilog/SystemVerilog design, simulation, synthesis, timing analysis, lint, CDC/RDC, UPF, DFT, verification support, analog collaboration, layout coordination, silicon evaluation, documentation, and debug. The role requires close collaboration across analog, verification, physical design, and broader product teams.

Defines power architecture and product roadmaps for data center products serving AI customers. Analyzes voltage regulator approaches, develops technical and executive collateral, supports strategic customer engagements, maintains key relationships, and drives cross-functional execution with marketing, design, packaging, applications, firmware, and software teams. The role requires deep semiconductor and power engineering expertise, including multiphase regulators, magnetics, passive components, power devices, embedded SoCs, and high-level modeling.

Develop and implement automated test solutions for analog and power management ICs. Responsibilities include defining test requirements, creating test hardware and PCB layouts, developing characterization and production ATE programs, correlating ATE results with bench measurements, conducting GR&R studies, troubleshooting signal issues, and transferring validated solutions into production for high-reliability space semiconductor applications.

Leads the architecture and full lifecycle development of analog, mixed-signal, and PMIC products from customer requirements through silicon verification and production readiness. Provides technical authority, mentors engineers, guides verification and DFT strategy, collaborates with customers and cross-functional teams, and drives engineering methodology improvements and roadmap planning.

Lead mixed-signal verification for automotive power management ICs, including PMICs, switching regulators, LDOs, and analog IP. Architect RNM and AMS environments, develop verification plans, debug analog and digital designs, optimize GLS flows, analyze PVT simulations, and maintain coverage and documentation. Collaborate with design, validation, CAD, ATE, and application engineering teams while improving verification methodologies and mentoring engineers.

Leads mixed-signal verification for automotive PMIC products, architecting RNM and AMS environments, verification plans, GLS flows, and RTL simulations. Debugs analog and digital systems across PVT corners, supports automotive safety compliance, and collaborates with design, ATE, application engineering, and silicon validation teams. The role also mentors junior engineers, improves verification methodologies and infrastructure, evaluates AI-based tools, and maintains verification documentation, test plans, and coverage.

Leads cross-functional semiconductor new product introduction programs from concept through market launch. Responsibilities include program planning, project gate reviews, capacity expansion, manufacturing and supply-chain coordination, ramp readiness, risk mitigation, qualification tracking, and leadership reporting. The role oversees wafer fabrication, assembly, testing, logistics, budgets, schedules, and global process standardization while driving alignment across engineering, operations, procurement, quality, and external manufacturing partners.

Leads architecture, design, implementation, validation, and roadmap development for DDR5 and DDR6 analog/mixed-signal PHYs. Manages a team of analog designers, oversees high-speed I/O, clocking, signal and power integrity, silicon bring-up, yield improvement, methodology, and signoff. Owns program execution, hiring, mentoring, cross-functional collaboration, foundry and vendor relationships, and long-term DDR technology planning.