Top Tech Jobs & Startup Jobs

Lead and scale site-wide digital design and verification for mixed-signal SoCs. Define verification strategy (SystemVerilog/UVM, formal, AMS/DMS), enforce RTL quality, timing closure, DFT, and sign-off criteria. Drive reuse, automation, metrics-driven verification, and on-time tape-out. Build technical teams, define career ladders, align cross-functionally, and translate product strategy into multi-year capability investments to improve first-pass silicon success and execution predictability.

Lead end-to-end execution of strategic customer programs for hyperscaler accounts: manage scope, schedules, NPI, engineering samples, volume ramps, supply coordination, cross-functional alignment, dashboards, risk mitigation, and customer/internal program reviews.

Lead end-to-end execution of strategic customer programs for hyperscaler accounts: manage scope, schedules, NPI, engineering samples, volume ramps, supply coordination, cross-functional alignment, governance, KPIs, and risk mitigation to ensure on-time delivery.

Lead end-to-end execution of strategic customer programs for hyperscaler customers: align scope, schedules, and deliverables; manage NPI, engineering samples, and volume ramps; coordinate supply chain and manufacturing; identify and mitigate risks; run cross-functional governance, dashboards, KPIs, and executive-facing status reviews.

Lead hardware/software bring-up of analog/mixed-signal and sensor ICs on customer MCUs/SoCs. Write driver-level firmware and application demos, debug full signal-chain issues, build reusable driver frameworks, document architectures and bring-up guides, lead technical integrations with partners, mentor engineers, and support customer lab demos and trade-show deadlines.

Lead global technical architecture and full development lifecycle for PMIC and analog/mixed-signal blocks. Collaborate with customers on system requirements, drive verification/DFT strategies, mentor engineers, and ensure production readiness while improving company-wide engineering methodologies and roadmaps.

Lead architecture and full development lifecycle of PMIC and mixed-signal analog blocks from specification through design, simulation, silicon verification, and production readiness. Serve as global technical authority, mentor engineers, collaborate with customers on system requirements, oversee verification/DFT and lab evaluation, and drive company-wide engineering methodology and roadmap improvements aligned with CMOS process trends.

Lead architectural evolution and full development lifecycle of PMIC and mixed-signal blocks, provide global technical authority, collaborate with customers on system requirements, oversee verification/DFT and lab evaluation, mentor engineers, and drive company-wide engineering methodology and roadmap improvements.

Lead design and development of advanced package and interconnect methods for power SiP/modules, WLCSP, flip-chip LGA and multi-chip modules. Drive wafer-level processes (Cu RDL, thinning, backside metal), define substrate and interconnect requirements, qualify materials and OSAT/CM processes, run DOE and SPC, resolve process integration issues, and support production ramp and quality for consumer, industrial, and automotive power applications.

Architects, designs, verifies, and optimizes CMOS analog blocks and high-speed DDR5/DDR6 I/O interfaces for custom ASICs. Analyzes silicon ATE and bench data, performs simulations, ensures signal integrity and circuit reliability, and collaborates with digital, systems, verification, validation, and test teams. Provides technical leadership and mentorship, documents designs, and ensures layouts meet analog matching and performance standards while satisfying power, area, and timeline constraints.