Top Tech Jobs & Startup Jobs

Senior technical authority defining and governing physical-design architecture and foundry strategy (TSMC) for MCU/SoC products. Leads AI initiatives to reduce MCU development cost, drives physical partitioning, PPA targets, IO and timing requirements, and aligns die-size and KPI goals with system architects and chip leads.

Lead cross-functional teams to manage end-to-end NPI programs for semiconductor power products, ensuring program planning, execution, ramp readiness, risk mitigation, and global process standardization. Coordinate wafer fabrication, assembly, test operations, supply chain, and stakeholders while providing regular leadership updates and driving scalability and disciplined execution.

Lead end-to-end delivery of derivative SoCs by combining RTL design, functional verification, and physical implementation. Build an AI-augmented silicon factory to predict physical outcomes during RTL coding, automate derivative generation and verification, and accelerate physical closure by reusing placement/routing and ML-driven optimizations.

On-site HR Business Partner supporting US business leaders and employees. Provide advisory on employee relations, performance, restructuring, talent planning, policy, and compliance. Drive employee experience, trends analysis, succession and retention planning, and collaborate with COEs, legal, and global HR to enable business objectives.

Lead development of high-performance switching power MOSFETs (12V–80V): design novel device structures, run TCAD simulations, define process flows, create mask/layouts, develop test/characterization methods, and collaborate with process integration and IC design teams to optimize manufacturability, reliability, and performance.

Design and optimize high-performance 12V–80V switching power MOSFETs across full product lifecycle. Use TCAD simulations, develop device structures and process flows, collaborate with fab/process engineers and IC teams, create test/characterization methods, execute layouts, and support product yield and reliability.

Lead cross-functional semiconductor NPI programs from concept to market launch, ensuring schedule, budget, quality, ramp readiness, and global process standardization. Coordinate design, validation, firmware, manufacturing, supply chain, and OSAT partners; conduct project gate reviews; identify and mitigate risks; drive capacity expansion, structured updates to leadership, and scalable program management practices.

Design and implement digital DFT (scan, ATPG, LogicBIST) for automotive PMICs, improve scan coverage, create and validate test patterns, run gate-level simulations, support synthesis/P&R/timing, and collaborate with architects, test, and validation teams to meet ASIL requirements.

Design and verify complex high-voltage analog and mixed‑signal block and sub‑system circuits for custom ASICs. Perform feasibility studies, AMS simulations, silicon debugging, lab characterization, and support test development and production ramp. Collaborate with project leads, layout, DFT, and test/product engineers; produce documentation and participate in design reviews to deliver differentiated solutions.

Serve as global lead for Honeywell and manage select Southeast accounts. Develop multi‑year sales strategy, drive design‑in/design‑win activities, lead cross‑functional teams, forecast revenue, align product roadmaps with customer needs, and resolve supply‑chain and commercial issues to maximize revenue and market share.