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Design and implement highly-configurable TileLink interconnects, cache controllers, protocol bridges and other uncore RTL generators using Chisel/Scala. Drive performance and coherence improvements, integrate into Chisel/FIRRTL framework, collaborate on verification plans and documentation, and work with teams to deliver high-quality, configurable IP for SoCs.

Design and implement CPU microarchitecture features and ISA extensions using Chisel. Integrate designs into Chisel/FIRRTL framework, perform sandbox verification, collaborate on verification plans, optimize for physical implementation and performance, and document microarchitecture specifications.

Architect, design and implement features for RISC-V CPU core generators using Chisel, with responsibilities in verification and performance modeling, collaborating with teams.

Design and implement CPU microarchitecture features and ISA extensions using Chisel; integrate into Chisel/FIRRTL framework; perform sandbox verification and collaborate with verification, physical implementation, and performance teams to meet frequency, area, power, and performance goals. Produce documentation and participate in collaborative design.

Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.

Architect and implement software and firmware for confidential computing on RISC-V/Silicon platforms. Collaborate with CPU/SoC/security teams, implement TEEs, virtualization and peripheral security solutions, write and review hardware/software specifications, and engage customers, partners, and standards bodies to drive platform security.

Develop and maintain the high-performance C++ application for an FPGA-hosted hardware emulation framework. Collaborate with FPGA RTL designers, compiler developers, and RISC-V engineers to enable fast, debuggable, and cost-effective emulation for software and hardware co-design.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

Lead a performance engineering team to research and develop high-performance processor architectures, defining targets and guiding implementation in RTL, while analyzing performance bottlenecks.

The Director of Sales for Commercial Accounts at SiFive is responsible for prospecting new accounts, creating account plans, managing CRM databases, and improving the sales process while achieving financial targets.