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Lead verification strategy and execution for advanced hardware prefetch in high-performance out-of-order CPU cores. Define test plans, checkers, assertions, coverage, and stimulus to validate prefetch training, stream management, request generation, DCache interactions, CSR configurability, and corner cases. Collaborate with architects, RTL, performance, and software teams; apply simulation, formal, emulation, and performance validation; drive debug, coverage closure, and mentor engineering teams to raise DV quality and reusable methodology.

Lead verification strategy and execution for CPU frontend in high-performance out-of-order cores. Define test plans, checkers, assertions, coverage, and stimulus for branch prediction, instruction fetch, redirects, recovery, and MMU/ITLB interactions. Partner with architects, RTL, performance, and verification teams, apply simulation, formal, and emulation methods, drive block- and core-level signoff, mentor engineers, and build reusable DV infrastructure and methodology.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

The Verification Architect at SiFive will ensure design fidelity for RISC-V based CPUs, develop verification strategies, and improve quality through collaboration with design teams.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel/FIRRTL). Improve multi-core coherence, integrate designs into toolchain, perform sandbox verification, collaborate with verification teams, and produce documentation and tests.

The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.

The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.

Design and implement TileLink interconnects, cache controllers, protocol bridges, and other uncore logic as configurable RTL generators (Chisel/Scala). Integrate designs into the Chisel/FIRRTL framework, enable automatic config/verification flows, perform sandbox verification, collaborate with verification teams, and produce documentation.