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The Strategic Sales Director is responsible for creating account plans, developing customer relations, and achieving sales targets within semiconductor companies. They must possess extensive experience in sales, specifically in IP sales, and be able to communicate effectively with clients.

Architect, design and implement features for RISC-V CPU core generators using Chisel, with responsibilities in verification and performance modeling, collaborating with teams.

The role involves analyzing and optimizing power consumption in SiFive IP, guiding architecture for power efficiency, and improving power analysis flows.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

Lead verification strategy and execution for CPU-subsystem power-management across unit, subsystem, and signoff levels. Define tests, assertions, coverage, and corner-case stress scenarios for DVFS, retention, clock/reset sequencing, power gating, and multi-domain interactions. Drive debug, root-cause analysis, formal and power-aware methods, reusable infrastructure, and mentor engineers to achieve data-center-grade signoff readiness.

Lead verification strategy and execution for advanced hardware prefetch in high-performance out-of-order CPU cores. Define test plans, checkers, assertions, coverage, and stimulus to validate prefetch training, stream management, request generation, DCache interactions, CSR configurability, and corner cases. Collaborate with architects, RTL, performance, and software teams; apply simulation, formal, emulation, and performance validation; drive debug, coverage closure, and mentor engineering teams to raise DV quality and reusable methodology.

Lead verification strategy and execution for CPU frontend in high-performance out-of-order cores. Define test plans, checkers, assertions, coverage, and stimulus for branch prediction, instruction fetch, redirects, recovery, and MMU/ITLB interactions. Partner with architects, RTL, performance, and verification teams, apply simulation, formal, and emulation methods, drive block- and core-level signoff, mentor engineers, and build reusable DV infrastructure and methodology.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

The Verification Architect at SiFive will ensure design fidelity for RISC-V based CPUs, develop verification strategies, and improve quality through collaboration with design teams.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.