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SiFive

Lead Debug/Trace/Profiling Design Engineer

Reposted 16 Days AgoSaved
In-Office
5 Locations
194K-237K Annually
Senior level
194K-237K Annually
Senior level
Software
Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.
Top Skills: ChiselRisc-VScalaSystem VerilogVerilogVhdl
SiFive Logo
SiFive

Intern - Platform Technology

Reposted 17 Days AgoSaved
In-Office
6 Locations
Internship
Internship
Software
As an intern, you'll design, build, and support design and verification languages and tools, focusing on language design, compiler implementation, and usability.
Top Skills: C++17F#HaskellLispOcamlScala
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