Linux Kernel Architect

Posted Yesterday
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12 Locations
In-Office or Remote
Senior level
Software
The Role
Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.
Summary Generated by Built In
About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

 

The Role

Do you want to be part of the RISC-V revolution? RISC-V and SiFive are redefining computing platforms for the 21st century.  SiFive, the world RISC-V leader, is seeking an experienced Linux kernel software architect.  In this role, you’ll be improving and debugging the RISC-V Linux kernel, with particular focus on high core count server systems.  You’ll interact directly with the upstream Linux and OpenSBI communities, posting and reviewing patches.  You’ll debug challenging problems, working with our system software and system validation teams, on SiFive designs running in emulation.  And you’ll work with hardware architects and engineers, both inside SiFive and at RISC-V International, to improve our core and system designs. 

What we need to see

  • Experience working on concurrency-sensitive code in the upstream Linux kernel, with a track record writing and reviewing patches on the public mailing lists

  • Experience debugging challenging software and hardware bugs in CPUs and SoCs

  • Experience working with CPU architects and RTL engineers

  • Experience developing and debugging Linux on FPGA and emulation platforms 

  • Experience with hypervisors and virtualization

  • Familiarity with the RISC-V architecture

Ways to stand out

  • Familiarity with silicon design issues and challenges

  • Familiarity with microarchitectural side-channel attacks and mitigations

  • Familiarity with debugging systems via hardware debuggers

  • Familiarity with Devicetree, ACPI and UEFI 

  • Familiarity with Rust

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

United States of America

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.

Skills Required

  • Experience working on concurrency-sensitive code in the upstream Linux kernel, with a track record writing and reviewing patches on public mailing lists
  • Experience debugging challenging software and hardware bugs in CPUs and SoCs
  • Experience working with CPU architects and RTL engineers
  • Experience developing and debugging Linux on FPGA and emulation platforms
  • Experience with hypervisors and virtualization
  • Familiarity with the RISC-V architecture
  • Experience interacting with upstream Linux and OpenSBI communities (posting/reviewing patches)
  • Successful background and reference checks and proof of right to work in the United States
  • Ability to comply with export-control requirements or obtain necessary export licenses/approvals
  • Familiarity with silicon design issues, microarchitectural side-channel mitigations, hardware debuggers, DeviceTree, ACPI, UEFI, or Rust
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The Company
HQ: Santa Clara, CA
552 Employees
Year Founded: 2015

What We Do

The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.

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