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The Principal Physical Design Engineer will oversee end-to-end STA ownership, coordinating and executing design processes for connectivity ASICs while ensuring robust timing closure and collaboration with various engineering teams.

Drive customer success for Taurus Ethernet solutions through technical engagement, debugging complex issues, and collaborating with internal teams for product evolution.

Lead the development of AI-powered IP Lifecycle and Quality Assurance Platform, ensuring all IP meets integration standards, through advanced EDA tools and automated audits.

Support layout design of analog and mixed-signal blocks, perform LVS/DRC/PEX verification, assist floorplanning, placement, routing and matching, optimize layouts with circuit designers for performance and manufacturability, and document work for reviews and tape-out under mentorship.

Lead block- and top-level physical implementation for high-speed transceiver IPs: floorplanning, placement, CTS, routing, routing signoff, EM/IR and congestion analysis, timing closure, IP integration, ECO/tapeout support, and automation scripting to optimize area, power, and timing in advanced process nodes.

The Principal Digital Design Engineer will architect and implement advanced digital designs for AI connectivity, manage complex design blocks, and drive RTL implementations, ensuring production-quality silicon for high-speed protocols.

Lead RTL design and implementation for connectivity silicon blocks from microarchitecture through synthesis sign-off. Collaborate with architecture, verification, DFT, and physical design teams to achieve timing closure, CDC, lint, and low-power goals. Mentor engineers, debug pre- and post-silicon issues, and drive methodology for timely tapeouts.

Lead advanced packaging R&D for photonics products, defining process flows (wafer/panel/die), integrating EIC-to-PIC, qualifying materials and equipment, partnering with OSATs and vendors, and driving yield, reliability, PDKs, and packaging design rules for NPO/CPO products.

Lead formal verification for complex IP and SoC designs: create formal plans, develop assertions and properties, drive proof convergence, deploy verification flows and tools, mentor engineers, triage bugs, and support verification sign-off to ensure first-pass silicon success.

Lead DFT strategy and execution for multi-die PCIe switch products using 2.5D/3D packaging. Define test architecture, implement scan/ATPG/MBIST/LBIST, drive fault coverage targets, optimize production test and ATE costs, collaborate across design, packaging, validation, and manufacturing to ensure yield, reliability, and production ramp.