Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
We are seeking a motivated Analog Mixed-Signal Layout Intern to assist in the design and layout of high-performance analog and mixed-signal IP blocks. You will work closely with experienced layout and circuit design engineers to translate schematic designs into silicon, gaining hands-on experience with advanced technology nodes and CAD tools.
Key Responsibilities
· Assist in layout design of analog and mixed-signal circuits such as: Current mirrors, differential pairs, op-amps, bandgaps, comparators…
· Perform layout-vs-schematic (LVS), design-rule checks (DRC), and parasitic extraction (PEX) to ensure design quality and manufacturability
· Support floor planning, placement, routing, and matching for analog blocks following layout best practices (symmetry, shielding, guard rings, etc.)
· Work with circuit designers to optimize layout for performance, area, and reliability (minimize mismatch, noise coupling, IR drop).
· Document layout work and contribute to layout review checklists and verification reports.
Qualifications
· Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
· Basic understanding of analog/mixed-signal IC design concepts.
· Familiarity with EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics.
· Basic understanding of matching techniques, layout symmetry, and common centroid structures. Strong analytical and problem-solving skills.
· Eagerness to learn advanced layout methodologies for high-speed and low-noise analog design.
What You’ll Gain
· Exposure to industry-standard AMS design flows and tools.
· Opportunity to study high speed layout techniques.
· Mentorship from experienced Circuit and AM layout engineers.
· Hands-on experience with real design projects leading to tape-out.
Preferred Skills (Nice to Have)
· Experience with version control systems (e.g., Git, Perforce).
· Knowledge of CMOS, FINFET devices structure.
· Familiarity with analog layout techniques and parasitic extraction.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Basic understanding of analog/mixed-signal IC design concepts (current mirrors, differential pairs, op-amps, bandgaps, comparators).
- Familiarity with EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics.
- Basic understanding of matching techniques, layout symmetry, and common centroid structures.
- Ability to perform LVS, DRC, and parasitic extraction (PEX) and follow layout best practices (shielding, guard rings, symmetry).
- Strong analytical and problem-solving skills and eagerness to learn advanced layout methodologies for high-speed and low-noise analog design.
- Experience with version control systems (e.g., Git, Perforce).
- Knowledge of CMOS and FinFET device structures.
- Familiarity with analog layout techniques and parasitic extraction tools/flows.
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
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