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The Senior Director will lead product technical ownership, driving chip development, cross-functional leadership, and processes within a growing AI technology company.

Lead and define SoC-level verification strategy and execution across IPs and subsystems. Build and mentor a verification team, drive UVM/formal/emulation-based methodologies, integrate IP verification into system environments, ensure first-pass silicon success, collaborate with RTL/architecture/firmware teams, and represent verification with executives and customers.

Lead and define end-to-end verification strategy for complex SoC products, manage and mentor a verification team, drive UVM/formal/AI-augmented methodologies, ensure PCIe/CXL compliance and first-pass silicon success, and collaborate with RTL, architecture, and software teams for debug and performance optimization.

Lead RTL design and implementation for complex connectivity IP blocks from microarchitecture to synthesis sign-off. Partner with architecture, verification, DFT, and physical design to achieve timing closure and silicon readiness. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and ensure high-quality, PPA-focused deliverables for PCIe/CXL/Ethernet-based SoC integration.

Lead RTL design and implementation for complex interconnect blocks from microarchitecture through synthesis sign-off. Collaborate with architecture, verification, DFT, and physical design teams to achieve timing closure and silicon-quality deliverables. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and support tapeout schedules for PCIe/CXL/Ethernet and related high-speed interfaces.

Lead strategic customer engagements and commercial negotiations with hyperscalers and AI platform providers to convert opportunities into long-term agreements. Drive cross-functional alignment, create regional/segment playbooks, develop market insights, and implement scalable processes to accelerate revenue growth and strategic partnerships in the semiconductor connectivity and AI infrastructure space.

Lead the go-to-market strategy for PCIe signal conditioning products, driving market positioning, execution, and revenue growth while collaborating with cross-functional teams and mentoring staff.

Lead capacity planning and scenario modeling across product lines and manufacturing partners. Build and maintain ETL pipelines, API integrations, Oracle reports, and Power BI dashboards to surface shortages, capacity risks, and recovery plans. Produce 18-month rolling forecasts, run constraint-based production plans, and drive cross-functional initiatives to resolve bottlenecks. Support NPI ramps and communicate risks and recommendations to stakeholders and leadership.

The Sales Intern will develop regional sales plans, engage with customers, provide technical support, and forecast regional revenue in collaboration with teams.

The Senior Principal Digital Design Engineer leads digital design architecture for AI connectivity, guiding teams through design execution and cross-functional collaboration while mentoring engineers to ensure high-quality production deliveries.