Top Tech Jobs & Startup Jobs

Lead product marketing and go-to-market strategy for edge AI solutions serving robotics, drones, machine vision, and industrial automation markets. Define hardware and software positioning, gather customer requirements, shape roadmaps, enable sales and FAE teams, grow partner and developer ecosystems, and support Ambarella’s Developer Zone. Manage cross-functional initiatives, technical demonstrations, events, customer relationships, and partner programs, with up to 30% international travel.

Develop and optimize classical computer vision and neural-network ISP acceleration pipelines on Ambarella’s CVflow architecture. Port algorithms and models to NVP and GVP processors, improving compute performance, memory efficiency, latency, power consumption, and real-time edge performance. Collaborate with algorithm, systems, and hardware teams on embedded computer vision applications involving image processing, optical flow, and radar/LiDAR point clouds.

Design, implement, and test imaging and video algorithms and DSP microcode for Ambarella SoCs. Develop firmware, research and implement DSP algorithms, optimize CPU and memory usage, create hardware-block test code, and debug assembly. The role requires understanding computer architecture, video standards, image processing, neural network frameworks, software development practices, and cross-functional teamwork.

Develop highly efficient deep learning and computer vision algorithms for edge applications, including self-driving cars and humanoid robots. Responsibilities include designing, training, and optimizing Transformer models, researching multimodal large language models and embodied AI, and building vision systems. The role also involves applying computer vision methods such as object detection, tracking, segmentation, and vision-language modeling, alongside robot control and sensor integration using ROS 2.

Develop software tools for future Ambarella embedded processors used in computer vision and intelligent automotive applications. Design and implement compiler language features, performance optimization tools, and related development capabilities. Collaborate with scientists, architects, and software and hardware teams to optimize chip performance. Work independently within a small R&D team.

Supports senior circuit designers in designing, validating, and characterizing mixed-signal and analog IP blocks for SoCs, including PLLs, DLLs, SERDES, high-speed I/O, and data converters. The role provides exposure to advanced sub-14nm technologies, analog integrated circuit design, digital logic, Verilog coding, laboratory work, and signal integrity.

Design and verify Design-for-Test logic for complex SoCs, automate scan, compression, and MBIST flows, analyze fault coverage, and perform timing analysis for DFT modes.

Develop and debug verification testbenches, tests, RTL logic, random test generators, coverage monitors, checkers, assertions, and simulation-analysis tools for complex SoCs featuring DSP, computer vision, CPU, and coprocessor blocks.

Design and verify ASIC logic for edge AI vision processors, including video compression, image processing, neural-network accelerators, and processor cores. Develop RTL in Verilog and SystemVerilog, optimize designs for timing, area, and power, and create UVM-based testbenches, BFMs, test generators, coverage monitors, and verification plans. Support synthesis, front-end tool flows, chip bring-up, and testing.

Implements and verifies design-for-test features, including scan, compression, MBIST, LBIST, and streaming scan networks, for complex computer vision SoCs. Develops scan and memory-test patterns, analyzes clocking for at-speed testing, performs post-layout timing verification, supports ATE pattern bring-up, and assists with silicon production, failure diagnosis, and test optimization.