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Leads architecture, specification, transistor-level design, verification, layout supervision, validation, and production release of complex analog and mixed-signal IC subsystems. The role addresses power management, clocking, data conversion, advanced-node design, manufacturing test, and post-silicon characterization. It also guides senior engineers, leads technical reviews, resolves cross-functional issues, and supports product development and customer problem resolution.

Supports low-power DFT implementation and verification for SoC designs, including scan insertion, scan-chain verification, MBIST, rule checking, test-coverage analysis, and debugging. Develops Tcl, Python, and Shell scripts for automation, documents methodologies and results, and collaborates with RTL, DFT, design verification, and physical design engineers.

Explore AI/ML-assisted and self-adaptive memory design techniques for optimizing performance, power efficiency, robustness, and yield. Analyze memory assist methods, operating conditions, failure signatures, and process variations. Develop adaptive monitoring, prediction, voltage, timing, and read/write control techniques, then document, benchmark, and present the proposed architecture and design insights.

Design Verification Intern responsible for verifying digital and SoC designs. Develop test plans, reusable SystemVerilog/UVM testbenches, test cases, stimulus, checkers, and coverage metrics. Automate randomized testing, debug verification issues, perform root-cause analysis, and collaborate with design teams. The role focuses on semiconductor and IoT applications, with edge AI inference experience preferred.

Supports foundation IP development for edge AI SoCs through standard-cell circuit design, simulation, layout, characterization, and debugging. Uses Python, pandas, and scikit-learn to analyze timing, power, noise, and process-voltage-temperature data, identify outliers, and build predictive models that reduce simulation effort. The intern also performs DRC/LVS cleanup, investigates simulation mismatches, and documents findings for the IP team.

Supports block-level physical implementation for ultra-low-power SoC designs, including floorplanning, placement, clock tree synthesis, routing, timing closure, static timing analysis, power and signal integrity analysis, DRC/LVS closure, and automation scripting. Collaborates with RTL, verification, and physical design engineers while documenting results and learning industry-standard semiconductor design workflows.

Develop and test the Ambiqsuite SDK for Ambiq SoC devices and emulation platforms. Extend HALs, BSPs, and device drivers for new MCU platforms; create SDK examples and reliability test cases; investigate issues and propose solutions; and build Python automation scripts for SDK development, builds, and verification.

Own revenue and product margin planning, forecasting, and budget-to-actual analysis for semiconductor products and manufacturing operations. Build financial models and R&D investment business cases, including ROI, payback, and sensitivity analyses. Partner with Sales, Marketing, R&D, Manufacturing, Operations, Accounting, and executives to optimize margins, prioritize investments, explain financial performance, and support investor relations. The role includes periodic travel to Taiwan and occasional late-night calls.

Leads physical implementation of analog IC subsystems including PMUs, clocking, and data converters. Responsibilities include floorplanning, transistor-level layout, matching, shielding, parasitic extraction, LVS/DRC closure, tape-out, validation, production test support, and layout review. Collaborates with analog, digital, RTL, physical design, product, and applications engineering teams. This is an onsite role requiring five days per week.

Leads specification, architecture, transistor-level design, verification, layout supervision, validation, and manufacturing test for complex analog IC subsystems. Partners with architecture, RTL, product, applications, and marketing teams; resolves cross-block issues; supports customer and manufacturing challenges; and mentors senior engineers without formal management responsibility.