Staff Engineer, Analog Layout

Posted 24 Days Ago
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Singapore, SGP
In-Office
Expert/Leader
Hardware • Internet of Things • Software • Wearables • Semiconductor
Join the Team Powering the Future of Edge AI
The Role
Leads physical implementation of analog IC subsystems including PMUs, clocking, and data converters. Responsibilities include floorplanning, transistor-level layout, matching, shielding, parasitic extraction, LVS/DRC closure, tape-out, validation, production test support, and layout review. Collaborates with analog, digital, RTL, physical design, product, and applications engineering teams. This is an onsite role requiring five days per week.
Summary Generated by Built In

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.


Scope 

As the Staff Engineer, Analog Layout at Ambiq, you will drive the physical implementation of key analog subsystems, including PMUs, clocking, and data converters, translating circuit architecture into silicon-ready layout that meets performance, area, matching, and reliability targets. 

This role works closely with Analog Design and RTL/Physical Design teams to implement custom analog layouts that meet and exceed customer needs. Designs will be in leading-edge technologies, such as 22nm, 12nm, and beyond. 

The successful candidate will be a highly motivated team player who, through collaboration with designers and layout peers, will help everyone succeed. 

The person in this role will be well-rounded, having been through a number of design cycles. They will have layout-related experience across the full flow, from floorplanning and whiteboarding with designers, to detailed layout and parasitic extraction, to LVS/DRC closure and tape-out, through validation and production test support. 

This role will be onsite, and the candidate will be expected to have a presence on site 5 days a week. 

Responsibilities 

  • Partner with analog designers on chip-level and block-level floorplanning and layout strategy 
  • Drive layout architecture decisions to balance performance, matching, area, and reliability trade-offs 
  • Execute transistor-level analog IC layout, including critical matching, shielding, and parasitic-sensitive structures 
  • Lead layout for complex blocks and closely supervise or review layout work from other layout engineers 
  • Conduct layout design reviews and resolve action items generated as a result of these reviews 
  • Attend circuit design reviews to provide layout feasibility input and guidance to designers and other layout engineers 
  • Work with analog and digital designers to ensure layout meets circuit intent and interface requirements 
  • Own parasitic extraction, LVS, DRC, antenna, and fill closure for assigned blocks and top-level integration 
  • Support prototype chip bring-up and testing to help validate analog circuit blocks against layout-dependent effects 
  • Support development of manufacturing test plans where layout impacts testability (e.g., probe access, trim structures) 
  • Support Product Engineering to meet manufacturing/production needs related to layout and yield 
  • Support Applications Engineering on layout-related customer questions (e.g., matching, noise, reliability) 

Skills Required

  • Layout-related experience across the full flow, including floorplanning, detailed layout, parasitic extraction, LVS/DRC closure, tape-out, validation, and production test support
  • Experience executing transistor-level analog IC layout with critical matching, shielding, and parasitic-sensitive structures
  • Experience leading layout for complex analog blocks and reviewing or supervising other layout engineers
  • Ability to collaborate with analog and digital designers on floorplanning, layout feasibility, circuit intent, and interface requirements
  • Ability to work onsite five days per week

Ambiq Compensation & Benefits Highlights

  • Healthcare Strength — Health coverage is described as company-paid for medical, dental, and vision, with added mental-health support, an Employee Assistance Program, and HSA/FSA options. These elements indicate strong breadth and employer cost-sharing in core healthcare.
  • Retirement Support — A 401(k) plan with a defined company match is specified, alongside basic life, AD&D, and disability coverage. This combination points to meaningful support for long-term savings and financial protection.
  • Leave & Time Off Breadth — Time off includes PTO, a robust paid-holiday schedule plus a floating holiday, and a year-end company shutdown. These provisions suggest above-baseline time away from work.

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The Company
HQ: Austin, Texas
220 Employees
Year Founded: 2010

What We Do

Ambiq® enables intelligence (AI and beyond) everywhere by delivering the lowest-power semiconductor solutions for battery-powered edge devices. As a pioneer in ultra-low power SoCs, Ambiq empowers wearables, IoT, smart home, healthcare, and industrial products with always-on, energy-efficient intelligence. Backed by our SPOT® technology and global innovation leadership, Ambiq is shaping the future of edge AI.

Why Work With Us

Direct influence on silicon architecture Smaller, high-impact teams Hardware/software co-design in real time Faster technical decision cycles Visible ownership at Staff & Director level Austin-based collaboration culture

Ambiq Offices

OnSite Workspace

Building silicon and embedded AI systems requires tight collaboration across firmware, hardware, validation, and architecture teams. We believe the hardest engineering problems are solved through direct, daily collaboration.

Typical time on-site:
HQAustin, Texas
Taiwan
China
Singapore
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