Physical Design Intern

Posted 25 Days Ago
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Singapore, SGP
In-Office
Internship
Hardware • Internet of Things • Software • Wearables • Semiconductor
Join the Team Powering the Future of Edge AI
The Role
Supports block-level physical implementation for ultra-low-power SoC designs, including floorplanning, placement, clock tree synthesis, routing, timing closure, static timing analysis, power and signal integrity analysis, DRC/LVS closure, and automation scripting. Collaborates with RTL, verification, and physical design engineers while documenting results and learning industry-standard semiconductor design workflows.
Summary Generated by Built In

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.


Scope  

We’re looking for a Physical Design Intern to join our SoC team and help design, tape out ultra low power chips in advanced process nodes. In this role, you’ll gain hands-on experience with physical implementation tools, learn how to deliver best PPA designs, and work alongside experienced engineers to tape out ultra low power products. This internship is an excellent opportunity to apply what you’ve learned in class, explore industry-standard tools, and see how your work connects to the technology powering everyday devices. 

Responsibilities 

As a Physical Design Intern, you will:

  • Support block-level physical implementation for SoC designs
  • Assist with floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure
  • Run and analyze static timing analysis (STA) and help debug timing violations (setup/hold)
  • Help perform power, signal integrity, and IR drop analysis under guidance
  • Contribute to design rule check (DRC) and layout versus schematic (LVS) closure activities
  • Develop and maintain scripts (e.g., Tcl, Python, Shell) to automate recurring tasks
  • Document methods, results, and learnings; present progress to your mentor and team
  • Collaborate with RTL, verification, and physical design engineers to resolve implementation issues

Basic Qualifications 

  • Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
  • Completed coursework in several of the following areas:
    • Digital logic design
    • VLSI design / physical design / ASIC design
    • CMOS circuits
    • Computer architecture (preferred)
  • Familiarity with Verilog or VHDL and digital design concepts (timing, pipelining, clocking)
  • Basic understanding of physical design concepts such as placement, routing, timing closure, clock trees, and power grid planning
  • Comfortable working in a Linux/UNIX environment

Skills Required

  • Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field
  • Coursework in digital logic design, VLSI design, physical design, or ASIC design
  • Familiarity with Verilog or VHDL and digital design concepts, including timing, pipelining, and clocking
  • Basic understanding of physical design concepts, including placement, routing, timing closure, clock trees, and power grid planning
  • Comfort working in a Linux/UNIX environment
  • Coursework in computer architecture

Ambiq Compensation & Benefits Highlights

  • Healthcare Strength — Health coverage is described as company-paid for medical, dental, and vision, with added mental-health support, an Employee Assistance Program, and HSA/FSA options. These elements indicate strong breadth and employer cost-sharing in core healthcare.
  • Retirement Support — A 401(k) plan with a defined company match is specified, alongside basic life, AD&D, and disability coverage. This combination points to meaningful support for long-term savings and financial protection.
  • Leave & Time Off Breadth — Time off includes PTO, a robust paid-holiday schedule plus a floating holiday, and a year-end company shutdown. These provisions suggest above-baseline time away from work.

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The Company
HQ: Austin, Texas
220 Employees
Year Founded: 2010

What We Do

Ambiq® enables intelligence (AI and beyond) everywhere by delivering the lowest-power semiconductor solutions for battery-powered edge devices. As a pioneer in ultra-low power SoCs, Ambiq empowers wearables, IoT, smart home, healthcare, and industrial products with always-on, energy-efficient intelligence. Backed by our SPOT® technology and global innovation leadership, Ambiq is shaping the future of edge AI.

Why Work With Us

Direct influence on silicon architecture Smaller, high-impact teams Hardware/software co-design in real time Faster technical decision cycles Visible ownership at Staff & Director level Austin-based collaboration culture

Ambiq Offices

OnSite Workspace

Building silicon and embedded AI systems requires tight collaboration across firmware, hardware, validation, and architecture teams. We believe the hardest engineering problems are solved through direct, daily collaboration.

Typical time on-site:
HQAustin, Texas
Taiwan
China
Singapore
Learn more

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