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The Lead Software Engineer will develop business logic components for a hardware verification tool using C++ and Java. Responsibilities include ensuring performance and scalability, collaborating with global teams, and working in an Agile environment.

The Principal Solutions Engineer at Cadence will develop high-performance PERC decks. This role requires collaborating with customers and internal teams while focusing on advanced node PERC solutions. The position emphasizes programming and scripting in various languages and requires a solid background in Physical Design and Verification.

The Lead Product Engineer will trace customer requirements and deliver high-quality solutions, support product development using the Innovus tool, and validate advanced features while participating in customer meetings for advanced semiconductor technologies.

Cadence Design Systems is seeking a Principal Software Engineer to work on the Genus Synthesis Solution product, focusing on synthesis optimization algorithms for timing, area, and power design metrics. Responsibilities include algorithm design, validation, R&D support, and mentoring. Candidates must have 7-12 years of experience with strong C/C++ proficiency, UNIX/LINUX familiarity, RTL knowledge, and experience in language compiler and timing analysis projects.

The Lead Verification Engineer at Cadence is responsible for leading design verification projects, managing the entire process from concept to closure, and developing functional verification environments. A strong background in System Verilog and UVM is essential, along with experience in IP verification, particularly in memory IP.

The Principal Application Engineer will provide technical support for deploying Cadence's Jasper Formal Verification products, develop innovative solutions with sales teams, and ensure customer success through proactive support. Responsibilities include collaborating with R&D, leading projects, delivering training, and representing Cadence at conferences. The role requires significant customer interaction and occasional travel.

The successful applicant will be responsible for designing and developing high-performance, low-power Network on Chip products, focusing on hardware architecture, micro-architecture definition, and RTL design.