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Develop C/C++ compiler and runtime software for HDL-based hardware verification platforms. Build SystemVerilog compiler front-end capabilities, improve compiler performance and infrastructure, and contribute to simulation, synthesis, and runtime flows. Collaborate with geographically distributed engineering teams to enhance Cadence verification products.

Provides technical leadership for advanced-node semiconductor implementation programs from synthesis and netlists through physical design, signoff, and tapeout. Develops PPA optimization methodologies, investigates silicon and convergence issues, collaborates with R&D and customers, influences EDA tool development, and establishes reusable implementation practices. Mentors engineers, supports strategic customer engagements and presales activities, and drives innovation across timing, power, signal integrity, verification, SoC integration, and advanced packaging.

Develop compiler technology for the Cadence Palladium emulation platform. Responsibilities include solving large-scale compilation problems involving logic optimization, logic modeling, data structures, multithreading, and distributed computing. The role requires strong software engineering fundamentals, C/C++ proficiency, debugging, Linux/Unix development, and knowledge of hardware description languages.

Leads North American cloud business development, technical pre-sales, customer engagements, and go-to-market execution for Cadence’s EDA cloud solutions. Develops cloud product roadmaps, business models, and sales pipelines while collaborating with sales, IT, R&D, and ecosystem partners. Evangelizes AI-driven EDA tools and applies generative AI to improve customer interactions and pre-sales support. Translates customer and industry needs into cloud product strategies and business growth.

Interns develop customer-focused technical documentation for Cadence’s Custom IC and PCB EDA products. Responsibilities include creating instructional content, reviewing product messaging and software interfaces, producing feature videos and blogs, and collaborating with R&D and product engineering teams across regions to ensure technical accuracy.

Develop AI-powered tools for Cadence’s Stratus HLS platform using C++, Python, LLM agents, prompt engineering, and RAG. Build agentic pipelines, IDE extensions, and reusable AI workflows; evaluate models, improve quality metrics, and maintain production software. Translate specifications into tested designs, participate in reviews, document solutions, and collaborate with senior engineers and HLS experts.

Owns customer evaluations and production adoption of Cadence Stratus HLS, resolves complex technical issues, trains users, and translates customer feedback into product requirements. Partners with product management, R&D, field engineering, and sales to refine functional specifications, influence roadmap priorities, and improve product quality. The role requires digital hardware and RTL design expertise, C++, Linux-based EDA workflows, and familiarity with SystemC, HLS tools, scripting, and AI-assisted hardware design.

Leads customer-facing pre-sales and post-sales support for Cadence digital IC implementation and signoff products. Provides expertise in synthesis, place and route, design closure, timing and power signoff, STA, and SDC debugging. Conducts presentations, demonstrations, benchmarks, and technical evaluations; improves implementation flows using Tcl, Perl, and shell scripting; collaborates with R&D; supports business cases; and mentors junior engineers.

Supervise regional accounting activities in a shared-services environment, including financial close and reporting, balance-sheet reconciliations, cash management, fixed assets, lease accounting, statutory compliance, tax-audit coordination, payroll coordination, and support for local Brazilian operations. The role partners with global teams, ensures adherence to corporate policies, and manages accounting processes and deliverables across multiple entities.

Lead digital design engineer responsible for designing and integrating SoC IPs, developing microarchitectural specifications, performing lint, CDC, synthesis, and PPA optimization, and supporting verification and physical design teams. The role also involves creating synthesis constraints, debugging design issues, automating repetitive tasks with scripting, and collaborating across engineering teams.