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The Lead Design Engineer will perform design verification of ASICs, create test plans, develop functional coverage, and involve in post-silicon validation in a collaborative environment.

Intern in Digital Verification & Simulation supporting Cadence Verification IP and related tools. Provide customer technical support, root-cause analysis, test-case development, automation using TCL/Python, collaborate with R&D, and author application notes under mentorship.

The role involves designing, deploying, and operating enterprise networks, leading initiatives, troubleshooting, and collaborating on cross-domain programs.

Lead software engineering efforts in developing and optimizing AI-integrated features for the Cadence Virtuoso platform, collaborating across global teams.

Lead global HR M&A strategy and execution across mergers, acquisitions, divestitures and joint ventures. Drive due diligence, Day 1 readiness, organization design, talent assessment, retention, communications, and integration execution. Build HR M&A playbooks, governance, tools and metrics while partnering with executives, deal teams and cross-functional stakeholders to deliver scalable, high-impact transaction outcomes.

Build scalable, resilient agentic AI and LLM/ML solutions. Translate requirements into high-level and detailed architectures. Implement solutions using Python/C++ and ML frameworks, applying AI/ML fundamentals, data structures, algorithms, and distributed systems.

The role involves working on Celerity AI Solution related to various simulations, contributing to AI projects, preferably with a PhD and engineering background.

This role involves designing, developing, and maintaining PCIe/CXL AVIP/VB components, focusing on protocol functionality and performance, while collaborating with teams and supporting customers.

The Lead Digital Verification Engineer is responsible for verifying digital RTL and developing reusable verification components, contributing to all aspects of digital verification, and working with design teams.