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The IC Design Intern will learn analog and digital IC design for high-speed communication circuits, utilizing Cadence tools such as the Spectre spice simulator and Virtuoso layout tool. The role involves contributing to IC product development and gaining insights into design methodologies.
The Lead Solutions Engineer will develop DRC and FILL decks for semiconductor manufacturing, create QC patterns, write physical verification rules, and test these rules on customer designs, while troubleshooting and providing feedback to teams.
The Media and Analyst Relations Director will enhance Cadence's brand visibility through strategic media relations and crisis management. Responsibilities include developing and executing media strategies, managing a team, serving as a spokesperson, and leveraging an extensive network of press contacts.
The intern will gain hands-on experience by running EDA tools for physical design automation, providing feedback for improvements, and developing documentation for knowledge sharing. Responsibilities include tracking project schedules and participating in all phases of work.
The Software Engineer II will design, develop, and debug software related to static timing analysis, focusing on statistical analysis and signal integrity. Responsibilities include researching advanced algorithms and implementing solutions to enhance tool performance, with an emphasis on scalable algorithms in C/C++.
The Sales Technical Business Development Director at Cadence will focus on developing and managing strategic partnerships, enhancing market share, and driving sales through effective marketing initiatives. Responsibilities include planning business activities, promoting engagement with partners, executing public relations events, and analyzing program performance for ROI.
The Principal Digital Verification Engineer will architect verification environments for complex protocols, develop methodologies utilizing industry tools, create SystemVerilog assertions, collaborate with design engineers, and manage verification plans. Responsibilities also include developing automated regression environments and participating in technical reviews.
The Principal C++ Software Engineer at Cadence is responsible for designing and developing features for the Protium Prototyping Platform, collaborating with teams across geographies, and supporting key customers with implementation issues. The role involves algorithmic software development for FPGAs and demands strong CS fundamentals, a willingness to work in a fast-paced environment, and a focus on quality and innovation.
The Principal Design Engineer will lead major blocks of Memory PHY layout design, engaging in hands-on critical analog and high-speed layout blocks. Responsibilities include coordinating with circuit leads, layout contractors, and team members, as well as participating in layout reviews.
The Digital Design Engineer II will contribute to the Ethernet Controller IP Design and Verification team, focusing on developing industry-leading IP solutions. The role involves working on Ethernet systems design and verification, using methodologies such as Metric Driven Verification, and engaging with front-end design tools. The engineer will collaborate with teams globally to enhance product differentiation and reduce time to market.
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