Job Opportunity: Foundry PDK Design Enablement Engineer
Experience Level: 2–4 Years
Department: Methodology & Flow Enablement Group
Education: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field
Position Overview
We are seeking a highly motivated Foundry Process Technology, PDK & DTCO Engineer with 2–4 years of experience to join our process technology group. In this role, you will bridge the gap between process technology and design, driving next-generation semiconductor technology through cutting-edge path-finding methodologies. The ideal candidate possesses a strong foundation in PDK enablement, physical verification decks, process/design interaction electrical studies, Spice model understanding and design automation.
Key Responsibilities
- PDK Enablement: Validate, deploy, and maintain foundational PDK components specifically tailored for advanced technology nodes.
- Technology Study Activities: Conduct rigorous standard cell, SRAM, and custom circuit benchmarking alongside interconnect optimization to maximize power, performance, and area (PPA).
- Automation & Methodology: Design, develop, and maintain robust scripts and automated execution flows for PDK enablement/validation and PDK analysis.
- Collaborative Path-Finding: Partner closely with internal DTCO groups to turn advanced device architectures into reality.
Required Qualifications & Technical Skills
- Industry Experience: 2–4 years of hands-on experience in semiconductor technology analysis, foundry PDK enablement, and the co-optimization of PDK components like LVS, DRC, Parasitic Extraction, spice models. Strong understanding of PDK design enablement flows. Exposure to multiple foundry & nodes is a plus.
- Device Physics: Strong fundamental understanding of CMOS device physics, including advanced architectures like GAA (Gate-All-Around), FinFETs, and planar MOSFETs.
- Physical Verification & EDA: Deep knowledge of Layout Versus Schematic (LVS), Design Rule Checking (DRC), Parasitic Extractions, and Spice models at transistor level. Cadence based tool knowledge is a plus.
- Tooling Familiarity: Direct experience or high proficiency with Cadence-based tool suites is highly advantageous.
- Team Collaboration: Proven experience interfacing with core PDK development teams, technology enablement units, or advanced technology benchmarking groups.
Skills Required
- 2-4 years of hands-on experience in semiconductor technology analysis, foundry PDK enablement, and PDK component co-optimization
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field
- Strong understanding of PDK design enablement flows
- Strong fundamental understanding of CMOS device physics, including GAA, FinFET, and planar MOSFET architectures
- Deep knowledge of LVS, DRC, parasitic extraction, and transistor-level SPICE models
- Experience developing automation scripts and execution flows for PDK enablement, validation, and analysis
- Experience interfacing with PDK development teams, technology enablement units, or advanced technology benchmarking groups
- Experience with multiple foundries and technology nodes
- Proficiency with Cadence-based tool suites
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
