Responsibilities
- Drive low-power design and verification activities, including UPF modeling, multi-voltage domain design, and power-aware simulation/emulation
- Support customer projects on both functional verification and power validation
- Analyze and debug complex issues related to power intent, RTL design, and system integration
- Collaborate closely with global R&D teams to deliver and optimize technical solutions
- Guide customers to success by providing high-quality technical support and troubleshooting solutions
- Contribute to methodology development, knowledge sharing, and best-practice standardization
Requirements
- Bachelor’s degree or above in Microelectronics, Electrical Engineering, or related fields
- Experience in at least one of the following areas:
- Low-power design or verification (UPF/CPF/Power-aware verification)
- RTL design or verification (SystemVerilog/UVM preferred)
- Solid understanding of:
- SoC architecture and digital design principles
- Power management techniques (Power domains, Isolation, Retention, DVFS, etc.)
- Strong problem-solving and debugging skills in complex systems
- Good communication skills in English (both verbal and written), able to work in a global environment
Preferred Qualifications
- Experience with Palladium/Protium/hardware emulation platforms
- Familiarity with EDA tools and verification flows
- Customer-facing experience (AE/PE/Solution Engineer)
- Tape-out experience in SoC or ASIC projects
- Experience in power analysis and optimization
Skills Required
- Bachelor's degree or higher in Microelectronics, Electrical Engineering, or a related field
- Experience in low-power design or verification, including UPF, CPF, or power-aware verification
- Experience in RTL design or verification; SystemVerilog and UVM are preferred
- Understanding of SoC architecture and digital design principles
- Understanding of power management techniques, including power domains, isolation, retention, and DVFS
- Strong problem-solving and debugging skills in complex systems
- Good verbal and written English communication skills
- Experience with Palladium, Protium, or hardware emulation platforms
- Familiarity with EDA tools and verification flows
- Customer-facing experience as an AE, PE, or Solution Engineer
- Tape-out experience in SoC or ASIC projects
- Experience in power analysis and optimization
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
-
Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
-
Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
-
Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.








