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As a Software Engineer II, you'll apply machine learning expertise within an R&D team, focusing on scientific computing and innovative technology delivery.

The Lead Design Engineer will work on Verilog coding, RTL design, timing constraints, and simulation testing, while being familiar with various protocols.

Provide technical support in digital IC design, handling RTL-to-GDSII methodology, and assisting in mixed signal design evaluations.

Develop and debug bare-metal C firmware for DDR5 PHY on microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform RTL and silicon bring-up debugging, and use scripting and EDA tools for co-verification and simulation.

Provide technical sales support as a senior application engineer for signal and power integrity across IC, package, and PCB designs. Deliver workshops, demos, training, and onsite customer support; analyze customer environments and recommend EDA solutions using Cadence or competitive tools. Collaborate with sales, R&D, product engineering, and marketing to ensure customer success.

Lead design and optimize high-performance, multi-threaded core workflows and Qt-based GUI for a large-scale parasitic extraction platform. Integrate agentic LLM workflows, expose programmatic interfaces, ensure AI-driven actions sync with the UI, and profile/tune Linux desktop performance under heavy data loads.

Plan and implement test strategies for a SPICE simulator, create procedures, test cases, and regression test systems (with scripting), debug and troubleshoot software, and build AI agents to improve product qualification efficiency while collaborating with R&D, Product Engineering, and Release teams to ensure product quality.

Design-for-Test (DFT) engineer responsible for scan chain and compression insertion, MBIST/LBIST, ATPG pattern generation and verification, debugging failures, verifying ATPG testbenches, and collaborating across architecture, design, and customer teams. Work with JTAG/IEEE test standards and Cadence flows to meet test coverage and quality metrics.

Lead research, design, development, and validation of advanced nonlinear finite element analysis algorithms and solution capabilities for MSC Nastran/Marc. Implement, optimize, test, benchmark, and document FEA features; create verification models and automated regression tests; investigate defects and performance issues; support QA, release readiness, and cross-team collaboration while mentoring engineers and guiding architectural decisions.

Develop, train, evaluate, and productionize deep learning models (including GNNs) for crashworthiness, injury biomechanics, and electronic drop-testing. Implement model pipelines, perform data processing and algorithm research, and collaborate with development, QA, support, and international research teams using Python/C++ on Linux/Windows.