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Lead deployment of Portable Stimulus methodologies for complex SoC verification. Debug generation/solver and modeling challenges, collaborate with Cadence R&D, develop reference models and best practices, support software-driven verification, reuse across simulation/emulation/post-silicon, and contribute to AI-assisted verification workflows.

Design and lead secure software development lifecycle practices; integrate security tools (SAST/DAST/SCA) into CI/CD and artifactory; collaborate with DevOps and engineering to prioritize and remediate software vulnerabilities.

Lead enterprise AppSec and DevSecOps strategy, secure software architecture, and compliance (CMMC, NIST, ISO). Drive secure SDLC, CI/CD integration, cloud/container security, vulnerability management, software supply chain integrity, and report security posture to executives while managing AppSec and DevSecOps teams.

Lead AppSec/DevSecOps engineer focused on integrating security tooling (DAST, SAST, SCA) into source repos (Perforce, GitHub), CI/CD, and artifact repositories. Manage cloud and on-prem security controls (WAF, CDN), perform vulnerability assessments, penetration testing, attack surface management, incident response, and ensure compliance with security frameworks.

Implement and verify Palladium and Protium SOC designs: perform RTL synthesis, floorplanning, clock tree building and optimization, close timing/IR drop and physical verification, document designs for tape-out, and interface with front-end RTL and back-end verification teams.

Lead strategic co-selling, marketing and communications partnerships with Tier 1 ecosystem partners to grow joint business and channels. Develop partner programs, campaigns, events, and collateral; align executives and sales through training; generate qualified leads and product opportunities; nurture long-term relationships; track and report program performance and ROI.

Drive revenue growth across strategic accounts by identifying and advancing complex enterprise opportunities, building executive relationships, leading account and territory planning, maintaining forecast accuracy, and collaborating with field sales, technical teams, and leadership to align solutions and achieve quota, cross-sell, and retention targets.

The Sr Principal Product Engineer will lead STA product development, bridge customer needs with R&D, create specifications, and enhance tool quality. Key focus on Tempus timing tools and customer engagement.

Lead and execute functional design verification using SystemVerilog and UVM. Develop verification environments, test plans, and drive verification closure for complex designs. Mentor teams and coordinate environment planning; memory IP experience (DDR/HBM/GDDR) is a plus.

Develop and optimize advanced EDA software within the Virtuoso Heterogeneous Integration toolset. Design, debug, and scale EM/thermal/RC extraction and multi‑physics features, improve runtime and CPU/GPU utilization, apply ML/AI to automate workflows, and mentor junior engineers while delivering customer-focused solutions.