Top Tech Jobs & Startup Jobs

Develop and maintain foundry PDK components for advanced semiconductor nodes. Perform standard-cell, SRAM, custom-circuit, interconnect, and PPA technology studies. Build automation scripts and execution flows for PDK validation and analysis. Apply knowledge of CMOS device physics, GAA, FinFETs, LVS, DRC, parasitic extraction, and transistor-level SPICE models while collaborating with PDK, technology enablement, and DTCO teams.

Leads quarterly and annual consolidated income tax provision preparation under ASC 740, including deferred taxes, uncertain tax positions, valuation allowances, reconciliations, and SEC disclosures. Supports federal and state tax compliance, SOX 404 controls, process automation, tax policies, audits, tax planning, M&A, and special projects. Collaborates with Finance, Accounting, Legal, Treasury, auditors, and external advisors. Requires strong U.S. corporate tax expertise, CPA licensure, and 5–7 years of relevant experience.

The Deal Desk Finance Manager advises sales teams on deal structures and terms, providing finance input to maximize company value while supporting customers and cross-functional teams. The role partners with internal stakeholders to evaluate and structure commercial agreements. Compensation includes base salary, potential bonus, equity, and benefits.

Partners with North American Sales to structure customer deals, assess revenue recognition and fulfillment risks, manage pricing and discounts, and ensure compliance with financial policies. Leads forecasting for business segments, mentors a direct report, advises stakeholders on quote-to-cash processes, and supports finance-related operational changes, acquisitions, and process improvements.

Responsible for country-level financial accounting within the EMEA Controller Team, including monthly, quarterly, and year-end close, balance sheet reconciliations, financial statement preparation, fixed assets, lease accounting, audits, tax and VAT compliance, forecasting, cash management, SOX compliance, and M&A integration support. The role works across international finance teams and delivers accurate reporting under strict deadlines.

Architects, designs, and delivers high-speed analog and mixed-signal IPs for UCIe, PCIe, memory, and SerDes interfaces. Leads design closure across TX/RX, PLL, DLL, CDR, clocking, datapath, and I/O circuits. Directs complex cross-functional IP programs, mentors engineers, drives technical excellence, and may oversee staffing, risks, execution, and customer engagements. The role involves advanced technology nodes, silicon delivery, IP architecture, technology migration, and design reuse.

Responsible for developing the Pegasus DRC product, including case analysis, problem solving, validation, and documentation while collaborating with related teams.

Lead product engineering for Cadence’s Digital and Signoff Group, supporting software tools used in advanced chip design. Collaborate with R&D and customer engagement teams to influence product development, fulfill customer requirements, manage tool deployments, and track customer issues. The role requires electrical engineering expertise and 4–7 years of experience with industry-standard IR/EM analysis tools.

Leads development and maintenance of semiconductor placement algorithms and technologies. Designs, debugs, and enhances software applications on Unix/Linux platforms while optimizing quality of results, performance, power, and area. Collaborates with routing and optimization teams, conducts code reviews, and ensures scalability, thread safety, usability, and test coverage. Requires strong C/C++ development skills and experience with EDA back-end design flows.

Develop and deploy AI surrogate models for structural and process simulations, including stamping, composites, and laminated structures. Build physics-informed deep learning systems that predict finite element analysis results while preserving physical accuracy. Generate synthetic simulation data, integrate models into engineering workflows through APIs, and create validation pipelines measuring accuracy, latency, and failure modes against numerical solvers.