Top Tech Jobs & Startup Jobs

Design, build, and maintain infrastructure automation and virtualization platforms (Terraform, Ansible, Python) for on-prem and hybrid cloud. Manage CI/CD pipelines, optimise Nutanix/KVM/VMware platforms, monitor with Prometheus/Grafana/Datadog, support AWS/Azure integration, enforce policy-as-code and security hardening, and mentor junior engineers.

Lead hands-on synthesis, LEC, CLP, and power-intent flows for advanced ASIC and SoC designs. Debug Genus synthesis, Conformal LEC, constraint, and power-intent issues; write ECO scripts and timing or power constraints; support CLP sign-off; triage issues; and collaborate with physical design, DFT, and RTL teams to achieve design closure.

Design and scale automated testing and validation frameworks for AI/ML models, LLM applications, and agentic systems. Develop unit, integration, regression, performance, safety, and end-to-end tests; create evaluation datasets and benchmarking pipelines; integrate validation into CI/CD; and implement observability, telemetry, quality gates, and audit readiness. Collaborate with ML, MLOps, Product, and Security teams to improve reliability, safety, compliance, and production quality.

Leads validation of AI-generated semiconductor verification artifacts and workflows. Reviews UVM testbenches, assertions, coverage strategies, simulation, and formal verification outputs. Debugs customer verification issues, develops ground-truth datasets and benchmark test cases, validates EDA tool interoperability, and collaborates with AI and engineering teams to improve model accuracy and verification productivity.

Lead development of low-power verification software for Cadence Palladium and Protium platforms. Responsibilities include enhancing UPF debugging, event logging, violation detection, IEEE 1801 support, documentation, AI-assisted debugging tools, and unified workflows across emulation and prototyping environments. The role requires collaboration with R&D, product engineering, and applications engineering teams, along with strong debugging, C++ code comprehension, RTL language knowledge, technical writing, and communication skills.

Build and manage sales pipelines for Design IP technology across North American accounts. Drive market penetration, adoption, revenue, and strategic sales plans while managing complex $1M+ licensing deals. Collaborate with engineering, marketing, legal, finance, executives, and EDA sales teams. Develop customer relationships from startups to enterprises, articulate IP value propositions, negotiate contracts, meet revenue targets, and provide market feedback to product leadership.

Develop new software features, maintain existing product functionality, and profile and optimize performance. Collaborate with the team to meet product specifications. Preferred experience includes mesh-related algorithms, performance improvements, parallel computing, and mesh, EDA, or related application development.

Leads product engineering for high-speed UCIe and interface IP across pre-sales, SoC integration, verification, silicon bring-up, debugging, and customer deployment. Owns complex technical issue resolution, leads customer and cross-functional engagements, improves integration methodologies, mentors engineers, and drives product readiness and customer satisfaction.

Leads product engineering for high-speed SerDes and interface IP across pre-sales, SoC integration, silicon bring-up, customer deployment, and post-sales support. Owns complex technical issue resolution, customer design reviews, RTL and timing strategies, integration methodology improvements, and cross-functional execution. Serves as the primary customer-to-R&D interface, mentors engineers, drives product readiness, and applies AI-assisted workflows to improve debugging and data-driven decisions.

Develops frontend RTL and advanced physical IP for high-performance consumer PHYs and serial interface standards. Responsibilities include RTL implementation, low-power design, synthesis constraints, DFT, verification strategy, FPGA/Palladium testing, and cross-functional collaboration across analog, layout, backend, firmware, validation, and product engineering teams. The role also supports IP integration, QA, customer releases, and pre- and post-silicon applications.