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The Principal Design Engineer at Cadence is responsible for leading design verification projects, confirming complex designs are verified from concept to closure. This role requires extensive experience in functional verification fundamentals, test plan generation, and environment development using System Verilog and UVM.

The Principal Design Engineer is responsible for the integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems. This role involves resolving complex implementation issues, supporting integration reviews, performing simulations for functionality, and enhancing customer communication and experience.

The Principal Design Engineer at Cadence will lead development in custom accelerator SoCs and collaborate with computational simulation teams. Responsibilities include designing verification processes, creating and maintaining test-benches, and participating in IP delivery and SoC tape-out. Candidates must have robust debugging skills and experience in a cross-team environment.

The Lead Design Engineer will perform pre and post silicon Physical Layer Electrical Validation on High Speed SERDES IP. Responsibilities include designing hardware/software infrastructure, implementing rigorous test suites, debugging silicon issues, and generating test reports.

As a Principal Design Engineer at Cadence, you will lead the design of Analog Mixed Signal (AMS) for High-speed Memory PHYs. You will oversee subsystems, mentor team members, participate in technical discussions, and ensure quality and efficiency in AMS design.

The Principal Application Engineer will provide technical support in digital IC design implementation, demonstrate full APR flow capabilities, assist in customer engagements, and lead team members effectively with minimal instruction. Key experience in advanced node design and design tape-out is required.

Cadence is seeking a Sr. Principal Software Engineer to work on the design, development, and verification of verification IP tools. The candidate should have strong communication skills, domain experience, and proficiency in functional verification using SV/UVM.