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Perform cell, block-level layout, macro planning, and interconnect for integrated circuits. Produce compact layouts, work under a designer's supervision, and meet schedule and quality targets.

Lead verification of DDR4/DDR5 memory controllers and AXI interfaces: develop SystemVerilog/UVM environments, write directed and constrained-random tests, validate ECC/parity and protocol correctness, perform coverage and waveform debug, integrate VIPs, collaborate with design/post-silicon/firmware teams, and mentor verification engineers.

Design and maintain OS-agnostic C APIs for Ethernet switches and PHYs, implement digital features (aneg, QoS, PTP time-stamping, MACsec, traffic shaping), ensure MISRA-compliant code aligned with ASPICE/automotive safety, and develop automated API validation tests.

Develop and maintain OS-agnostic C APIs and MISRA-compliant drivers for physical Ethernet interfaces and PHYs, support PCS/MAC functionality, tune interfaces from MII to 1G–25G SerDes, contribute to switch drivers, and help build automated test infrastructure for automotive and industrial safety-critical applications.

Develop and maintain technical documentation for FPGA and SoC products, including user guides, reference manuals, application notes, workflows, diagrams, and illustrations. Collaborate with engineering and product teams to explain RTL design, simulation, synthesis, timing analysis, protocols, and hardware validation. Manage documentation deliverables, apply DITA and style-guide standards, use authoring and collaboration tools, meet aggressive deadlines, and improve technical publications processes.

Own verification for complex blocks and subsystems within ARM-based SoCs. Develop SystemVerilog and UVM test environments, create test plans and constrained-random tests, manage regressions, analyze code and functional coverage, debug RTL and testbench issues, and collaborate with architects and validation teams. The role also contributes to automation initiatives, methodology improvements, cross-site program leadership, and mentorship of junior engineers.

Lead architecture, RTL design, and verification of multi-gigabit Ethernet PHY digital blocks using industry-standard ASIC flows. Perform RTL coding, functional verification, pre-silicon FPGA emulation, synthesis/STA, and coordinate silicon bring-up while mentoring junior engineers and collaborating with cross-functional global teams.

Lead chip-level design and verification for Touch Controller IPs, from specification and architecture through RTL implementation and verification. Contribute to design reviews, documentation, development methodology, project coordination, and cross-functional collaboration.

Provide technical support and training for USB products, debug customer hardware/software implementations, develop evaluation hardware and reference designs, create documentation and application collateral, and collaborate with product marketing and partners to guide product development.

Designs, integrates, validates, and debugs FPGA-based platforms supporting USB and Ethernet PHY products, mixed-signal IP, and SoC solutions. Responsibilities include RTL coding, simulation, synthesis, timing analysis, place-and-route, multi-clock-domain design, performance optimization, board-level bring-up, laboratory debugging, system integration, documentation, and automation of FPGA development flows. The engineer collaborates with digital, analog, hardware, firmware, software, ASIC, verification, and validation teams.