Principal Engineer- Design (FPGA)

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Job Description:

Microchip’s NCS Team is seeking an experienced FPGA Design Engineer to support PHY (Physical Layer) development and system-level solutions for our next generation of USB and Ethernet products. The role will involve working closely with digital, analog, and software engineers to develop, integrate, and validate FPGA-based platforms supporting mixed-signal IP and SoC products.

The candidate must be located in the Chandler Design Center.

Requirements/Qualifications:

• 10 years or more of experience in FPGA and/or digital design, with solid hands-on experience in RTL coding, simulation, synthesis, and hardware implementation.

• Strong proficiency in Verilog and/or SystemVerilog for synthesizable RTL design.

• Strong understanding of digital design fundamentals, including state machines, datapaths, pipelines, clocking, resets, FIFOs, memories, and interface logic.

• Hands-on experience developing self-checking testbenches and performing functional simulation and debug using tools such as QuestaSim/ModelSim or equivalent simulation environments.

• Hands-on experience with FPGA synthesis, implementation, timing analysis, and place-and-route using vendor design environments such as AMD/Xilinx Vivado.

• Ability to define and analyze timing constraints and experience designing systems containing multiple clock domains.

• Experience optimizing FPGA designs to achieve required performance, area/resource utilization, and target clock frequencies.

• Experience with FPGA system integration and board-level bring-up, including loading FPGA images, exercising hardware interfaces, and debugging designs on physical circuit cards.

• Hands-on experience using laboratory debug equipment such as oscilloscopes, logic analyzers, protocol analyzers, and FPGA embedded logic-debug tools or equivalent.

• Ability to work closely with hardware, firmware, software, ASIC, analog, verification, and validation teams during system integration and lab bring-up.

• Experience in USB and Ethernet PHY architectures and protocols is a strong plus.

• Provide clear design documentation, including requirements, FPGA architecture, block diagrams and interface control documents.

• Proficiency in scripting languages such as TCL, Python, Perl. Linux shell programming or programming languages such as C++ or RUST for automating FPGA build, simulation, synthesis, and implementation flows.

• Knowledge of revision-control systems such as Perforce, Git, DesignSync, or equivalent, including experience with tagging, branching, configuration management, and release methodologies.

• Must possess strong verbal and written communication skills and be able to participate effectively in technical discussions and design reviews, provide project updates, and develop functional and technical documentation.

Travel Time:

Physical Attributes:

Physical Requirements:

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