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Lead the firmware development for AI accelerators by architecting control logic, optimizing data movement, and mentoring teams.

The Chief of Staff will support the Group President by managing operational activities, leading strategic planning, and representing the executive in corporate forums. This role requires strong problem-solving skills, experience in semiconductor products, and an AI-first mindset to modernize workflows.

Design and verify complex CMOS analog and mixed-signal IP (bandgaps, amplifiers, LDOs, PLLs). Use Cadence and AMS/Spectre/SPICE tools, perform lab debug, post-silicon validation and characterization, develop DFT strategies, document designs, and collaborate with test, product, and applications teams to deliver production-ready IP on schedule.

Manage product change, lifecycle, and product data for AMG and ISG business units. Support PCN process from creation through customer release, coordinate PLM and PDM activities, maintain PDM accuracy, analyze portfolios for end-of-life and reactivation, collaborate cross-functionally to implement improvements and maximize savings.

The Staff Analog Design Engineer will define architectures for analog/mixed-signal components, lead design projects, and collaborate across teams for successful production release.

Lead digital architecture and RTL teams for power-management ASICs, owning design, verification, synthesis, timing, low-power strategies, and tool flows. Collaborate cross-functionally, support pre- and post-silicon validation (FPGA, emulation, SoC platforms), and implement process and tool improvements for complex PMIC, DC-DC, AC-DC, LED driver and multiphase controller designs.

The GaN/BCD/Power Device Process Integration Engineer develops and optimizes GaN/BCD power devices through process integration, yield analysis, and project management, collaborating with R&D and foundries to ensure manufacturability and quality.

Design and execute constrained-random verification environments and testbenches for digital top-level subsystem IP on the TREO platform. Implement scoreboards, monitors, stimulus generators, checkers, and coverage-driven closure. Integrate formal verification, debug system-level mixed-signal issues, collaborate with digital/analog teams and architects, and improve verification strategy, reuse, and scalability using tools such as Questa.

The Process Engineer will support the development of new technology platforms and processes, working collaboratively with cross-functional teams in semiconductor manufacturing and data analysis.

The Senior Lithography Engineer will optimize lithography processes, execute experiments, drive yield improvements, and support production operations with data analysis and team collaboration.