Top Tech Jobs & Startup Jobs

Lead and execute backend digital physical design for SoC at 5nm and below, covering floorplanning, placement, CTS, routing, extraction, STA, ECOs, physical verification, and automation of EDA flows to achieve timing closure and right-first-time silicon.

Work on full-chip physical design: floorplanning, partitioning, placement, CTS, routing, and physical verification (LVS/DRC/ERC/Antenna). Perform STA, equivalence checks, crosstalk/noise analysis, power optimization, timing/functional ECOs, and formal verification. Drive congestion resolution and timing closure, mentor team members, collaborate globally, and adopt new tools/methodologies.

Perform SOC physical design at block level including floorplanning, partitioning, placement, clock tree synthesis, routing and physical verification (LVS/DRC/ERC/Antenna). Execute STA, equivalence checks, crosstalk and noise analysis, power optimization, and implement timing/functional ECOs. Use formal verification and timing analysis to achieve congestion, timing and area metrics. Mentor team members and collaborate in a global, dynamic environment while adopting new tools and methodologies.

Lead and execute backend digital physical design for SoC at 5nm and below, including floorplanning, placement, CTS, routing, extraction, PV, STA closure, timing/functional ECO, and automation of EDA flows across Cadence/Synopsys/Mentor toolchains.

Design and develop integrated circuits and ASICs across architecture, logic, verification and documentation. Drive system simulation, synthesis, place-and-route, timing and power analysis, and complex IC layout. Lead projects, mentor junior engineers, evaluate process flow and vendor capabilities, and champion product development from high-level design through tape-out.

Design and implement chip-level DFT architecture and basic DFT schemes (scan, boundary scan, Mem/Logic BIST). Verify DFT logic and test patterns via simulation, perform static timing analysis for test modes, and support ATE bring-up and debug of DFT patterns.

Customer-facing role designing, validating, and deploying VMware Kubernetes Service on VMware Cloud Foundation. Lead technical discovery, workshops, and proofs-of-concept; produce reference architectures; collaborate with sales, product, and engineering to drive adoption and guide modernization, scalability, security, and DR strategies. Travel up to 50%.

Design and debug high-speed board-level hardware, focusing on signal/power integrity and controlled-impedance implementations. Work with DDR, PCIe, SerDes, oscilloscopes and spectrum analyzers in lab, collaborate in teams, and communicate technical results clearly. Requires strong analog and digital board-design knowledge.

Perform SOC physical design including block-level floorplanning, partitioning, placement, CTS, routing and physical verification (LVS/DRC/ERC/Antenna). Drive STA, equivalence checks, crosstalk/noise analysis, power optimization and implement timing/functional ECOs. Mentor team members, work in global teams, and use/learn EDA tools for timing closure and congestion resolution.

Lead advanced packaging R&D for multi-chip AI/HPC modules. Define technology roadmaps, drive assembly process development and qualification, perform failure analysis and yield/parametric data analysis, run thermal/stress simulation, manage projects through transfer to high-volume manufacturing, and coordinate with foundries, OSATs, and internal design/validation teams.