Top Tech Jobs & Startup Jobs

Lead SATAS program integration and operations: own weekly syncs, dashboards, trackers, and meeting cadence; coordinate cross-functional swimlanes (equipment, automation, AMHS, MES, pilot-line readiness); manage risks, dependencies, and executive reporting; drive sustainability and operational-readiness activities; prepare executive updates and establish repeatable operating mechanisms to ensure program deliverables and alignment across Intel, Japan partners, and suppliers.

Lead security architecture for Client and Data Center SoCs, using AI-driven tools to discover firmware and low-level vulnerabilities, define firmware security specifications, drive threat modeling, partner with architects and engineers to translate risks into mitigations, and mentor engineers to operationalize AI-enabled security discovery across products.

Develop and enable CMP planarization processes for semiconductor manufacturing. Lead process design, equipment and consumables selection, feasibility studies, supplier partnerships, and production optimization to meet device specs and roadmap goals.

Lead substrate supplier development and qualification for advanced packaging (FCBGA, EMIB-T, glass core). Drive technical enablement, process development (SPC, DOE, FMEA), supplier readiness, factory validation, and ramp activities while coordinating cross-functional teams and supplier sites.

Lead physical implementation of custom CPU designs from RTL to manufacturing. Execute floorplanning, synthesis, place-and-route, clock tree synthesis, STA, power/clock distribution, verification and signoff. Collaborate across architecture, logic, circuit, CAD, and validation teams to optimize power, performance, area, and manufacturability, improve physical design methodologies, and work with EDA vendors to advance tools and automation.

Lead experimental research to develop semiconductor process modules: design, execute, and analyze experiments; develop chemical processes; integrate process steps for complex microprocessors; ramp technologies to manufacturing volumes and transfer via Copy Exactly Methodology; contribute to IP and cross-functional project leadership.

Develop, validate, and maintain PERC ESD and LU rule decks and methodologies. Collaborate with design, reliability, CAD teams and EDA vendors; build test cases, debug rules, define QA and automation, and drive cross-team solutions and tool enhancements for PDK reliability and ESD verification.

Develop mixed signal and high-speed IPs by writing RTL code, performing simulations, optimizing designs, and supporting SoC customers for high-quality integration.

Design and develop RTL logic for SoC blocks, integrate IP and subsystems, optimize for power/performance/area/timing, ensure quality for physical implementation, apply secure hardware development practices, and collaborate with IP providers to validate SoC designs.

Develop and validate test programs for wafer sort, unit class, burn-in and parametric testing. Define test plans, debug results, coordinate with design, yield, foundry, and test operations, and improve tester/tool performance.