Top Tech Jobs & Startup Jobs

The CPU Power Architect will define CPU power management architecture and solutions, coordinating new designs and ensuring efficient power delivery and management.

Develops and optimizes semiconductor packaging processes and equipment to improve quality, reliability, yield, productivity, cost, and manufacturability. Applies SPC and DOE, designs reliability-testing equipment, defines material specifications, collaborates with suppliers and procurement, leads technical problem solving, and establishes qualification and manufacturing quality systems for advanced packaging technologies.

Designs, develops, simulates, verifies, and optimizes analog and mixed-signal circuits, including GPIO, PLLs, LDOs, and ADCs, for advanced semiconductor process nodes. Responsibilities include floor planning, parameter extraction, test planning, performance analysis, issue resolution, and power, performance, area, timing, and yield optimization. The role collaborates with architecture and layout teams to deliver robust, high-quality semiconductor IP.

Leads the translation of business and customer requirements into scalable digital experiences for Intel Edge AI and Robotics platforms. Defines user journeys, information architecture, wireframes, UX standards, acceptance criteria, and production-ready specifications. Partners with stakeholders and development teams to prioritize capabilities, review delivered functionality, improve usability, and support AI-assisted search, recommendations, chatbots, and guided workflows.

Lead end-to-end architecture for modular, scalable SoCs supporting datacenter and agentic computing. Define hardware, firmware, functional specifications, microarchitectures, registers, and performance goals; integrate IP blocks; develop validation infrastructure; analyze benchmarks; and optimize power, timing, performance, and area. Collaborate across architecture, design, systems, and verification teams, influence technology roadmaps, provide technical leadership, and mentor other engineers.

Conduct semiconductor process integration research involving device physics, materials, transistor structures, process flows, experiments, and characterization. Develop process solutions that improve performance, reliability, scalability, yield, and manufacturability. Collaborate with engineering, research, manufacturing, suppliers, and academic partners; analyze electrical and physical data; address equipment and process issues; and transfer technologies from research into development and high-volume manufacturing.

Develops strategic partnerships and enterprise opportunities for Intel-based Physical AI and robotics solutions. Builds adoption strategies, business cases, go-to-market plans, account plans, and co-sell motions with cloud providers, systems integrators, software partners, robot OEMs, and AI model providers. Positions Intel technologies, represents market needs internally, influences product roadmaps, and drives ecosystem-led deployment scale across industries.

Designs and supports EDA methodologies, custom design infrastructure, automation frameworks, and verification flows for semiconductor testchip development. Develops SKILL, Python, and scripting-based solutions for layout generation, library management, data migration, and design-flow optimization. Enables CAD environments, version control, and database infrastructure while collaborating with engineering teams on full-chip integration, DRC/LVS verification, tape-in readiness, and silicon characterization.

Own and optimize semiconductor manufacturing processes and equipment to improve safety, quality, productivity, yield, reliability, and cost. Analyze production data, conduct experiments, investigate root causes, implement corrective actions, and support new technology qualification and factory ramp activities. Collaborate with manufacturing, process and equipment engineering, quality, suppliers, and global stakeholders while developing documentation, dashboards, and continuous improvement initiatives.

Designs and develops analog and mixed-signal circuit IPs in advanced process nodes. Responsibilities include circuit design, floorplanning, simulation, behavioral modeling, parameter extraction, test planning, verification, and optimization for power, performance, area, timing, leakage, and yield. Collaborates with architecture and layout teams to resolve design issues and improve circuit robustness.