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Lead end-to-end physical implementation of complex ASIC blocks from RTL to tape-out. Drive synthesis, place-and-route, and timing closure to meet PPA goals, collaborate with frontend/IP/CAD teams, advance physical design methodologies, and provide technical direction and mentorship to deliver production-ready silicon.

Designs, architects, and verifies high-performance ASICs and subsystems. Develops reusable verification code and methodologies, debugs at ASIC/SW/HW levels, leads block- and chip-level issue resolution, collaborates with mixed-signal and system teams, supports lab bring-up, implements PD EDA flows and physical design for complex blocks, and defines power and signaling solutions for high-volume products.

Open-position administrative support role for candidates with a disability certificate. Duties include event planning and operations, attendance data analysis and reporting, HR/labor support, and general office/marketing/finance/SE/sales-support tasks. Contract employee (1-year renewable) with potential for permanent hire. Requires basic PC skills and strong Japanese communication; remote work available.

Lead design, develop, and maintain the Device Automation/ServiceNow platform. Collaborate with cross-functional teams to translate requirements, build integrations, run system testing, monitor platform health, create scripts/workflows, troubleshoot issues, and provide end-user training and support.

Provide Mandarin-language first-line remote support for Cisco employees on macOS and iOS. Troubleshoot upgrades, MDM enrollment, authentication, VPN, networking, peripherals, and applications; document cases, monitor issue trends, escalate to engineering, and participate in escalation/change programs.

Perform FEA and thermomechanical simulations of ASICs and advanced packaging to evaluate stress, warpage, and solder joint reliability. Automate workflows, correlate predictions with test data, support early-phase design optimization, failure investigations, and present analysis and design recommendations to cross-functional global teams.

Develop and optimize CAD methodologies and flows for ASIC physical design from RTL to GDS. Work on physical synthesis, place-and-route, timing closure, floorplanning, and verification. Integrate and validate PD EDA tools, support technology adoption, and improve backend processes to deliver high-quality VLSI designs.

Lead and review micro-architecture and verification plans, supervise verification engineers, implement UVM-based environments, collaborate with design and firmware teams to debug, close coverage, and perform post-silicon validation and root-cause analysis in the lab.

Join Cisco Webex Media in Stockholm to build real-time media features, write performant C/C++ code, participate in agile development, perform peer reviews, automate workflows, and collaborate across teams to grow technical and soft skills.

Lead full-chip physical design: floorplanning, partitioning, pin/bump assignment, clock planning, power-grid planning, place-and-route, STA, power integrity, physical verification and equivalence checks. Improve EDA flows, collaborate with RTL/DFT/package/foundry/IP teams, use UPF for low-power design, and apply Python and AI tools to boost productivity.