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Participate in a 12-month new graduate program while owning semiconductor product engineering launch activities. Responsibilities include pre- and post-silicon development, sample buildup, silicon validation, characterization across voltage and temperature conditions, manufacturing milestone tracking, yield analysis, DOE, Gage R&R, and production test limit development for ESD, TVS, and surge protection devices.

Supports high-volume semiconductor manufacturing by selecting, installing, upgrading, maintaining, and improving CMP equipment. Analyzes equipment performance and reliability, performs lot and equipment dispositions, develops uptime and problem-resolution solutions, supports repair and process engineering teams, and defines preventive maintenance schedules. The role requires collaboration across manufacturing functions in a 300mm wafer fabrication environment, with emphasis on equipment reliability, production continuity, cycle-time reduction, and semiconductor cleanroom practices.

Develop, characterize, simulate, and optimize BiCMOS SiGeC HBT devices for RF and mm-wave volume production. Lead process and device simulations, experiments, RF/DC characterization, data analysis, and manufacturability improvements while collaborating across integration, reliability, packaging, circuit design, test, and product teams. Manage multiple technical projects, schedules, stakeholder communications, and cross-functional engineering efforts.

Process high-volume vendor invoices, perform three-way matching, resolve discrepancies, execute payments across countries and currencies, respond to vendor inquiries, reconcile statements, and maintain accurate financial records. The role requires compliance-focused execution, strong attention to detail, independent problem-solving, deadline management, and collaboration with internal and external partners. Fluency in English and German is required; Spanish is a plus.

Develop coverage-driven verification plans and mixed-signal testbenches for analog and digital ICs. Create behavioral models using Verilog-A, Verilog-AMS, Wreal, or EENet; implement analog checkers and assertions; execute RTL and gate-level simulations; manage regressions and coverage through tape-out; and collaborate with system, analog, digital verification, design, and post-silicon validation teams to debug issues and deliver products.

Designs and architects analog ICs and power-management circuits from definition through manufacturing release. Responsibilities include circuit design, simulation, verification, layout oversight, silicon evaluation, customer interaction, technology roadmap development, and cross-functional collaboration with process, packaging, validation, test, and applications teams. The role also provides technical leadership, guides team members, supports hiring and development, and ensures high-quality, manufacturable designs meet customer requirements and schedules.

Develops and implements semiconductor production test methods, processes, fixtures, and ATE software. Troubleshoots test, quality, and device-performance issues using analog circuit analysis and ATE expertise. Performs yield analysis, robustness and correlation testing, and supports multi-factory manufacturing and assembly flows. Collaborates with fabs and cross-functional teams to improve yields, optimize test costs, and deliver next-generation test solutions.

Leads semiconductor production test and silicon validation activities from definition through manufacturing release. Develops ATE test processes, fixtures, and software; troubleshoots circuit, quality, and device-performance issues; analyzes yield and test robustness; supports multi-factory manufacturing flows; and guides project teams through schedules, technical objectives, and customer-facing reviews.

Design and integrate RTL for automotive MCU subsystems and SoCs, including ARM-based CPU, low-power, reset, and clock-management systems. Responsibilities include defining microarchitecture, collaborating with IP, architecture, verification, DFT, emulation, and physical implementation teams, and supporting debug, design reviews, timing analysis, formal verification, and industry-standard front-end design flows.

Develop and execute comprehensive digital design verification strategies for analog and mixed-signal ICs. Build UVM testbenches, run RTL and gate-level simulations, manage regressions and coverage closure, and debug complex design issues. Apply formal verification, CDC/RDC assertions, low-power verification with UPF, and protocol checks. Support post-silicon characterization and ATE pattern generation while collaborating with architecture, design, firmware, product, and application engineering teams.