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Owns end-to-end functional verification of an AI-native DSP SoC, including verification planning, UVM testbench development, interface integration, datapath validation, DMA, interrupts, clock/reset, power, DFT, regression, coverage closure, gate-level simulation, tapeout sign-off, and post-silicon support. The role requires commercial SoC tapeout experience, full-chip verification ownership, and expertise across wireless, AI, video, camera, and radar workloads.

Owns end-to-end semiconductor and SoC/ASIC programs from planning through silicon tape-out and post-silicon validation. Coordinates architecture, design, verification, physical design, DFT, firmware, and validation teams while managing milestones, dependencies, risks, vendors, foundries, customers, and strategic stakeholders. Provides executive status reporting, drives issue resolution, and ensures timely program delivery.

Plan, design, survey, deploy, commission, and optimize LTE, 5G small cell, and private 5G networks. Responsibilities include RF coverage and capacity planning, link budgets, propagation modeling, interference analysis, site surveys, drive and walk testing, KPI analysis, performance optimization, and technical reporting. The engineer will collaborate with customers, government agencies, and internal teams on smart city, industrial, and government network projects.

Own end-to-end SoC implementation and tapeout, including IP integration, clock/reset and power architecture, synthesis, timing closure, lint, CDC, formal equivalence, power analysis, DFT, ECOs, sign-off, foundry handoff, and post-silicon bring-up. The role requires commercial tapeout experience at 22nm or below, direct sign-off ownership, and expertise with advanced semiconductor design tools, FinFET nodes, and high-speed peripheral integration.